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De Francesco" To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, Davidlohr Bueso , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Dan Williams , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] cxl: docs/driver-api/conventions resolve conflicts btw CFMWS, LMH, ED Date: Fri, 04 Jul 2025 15:11:16 +0200 Message-ID: <8767023.EBGB3zze1k@fdefranc-mobl3> In-Reply-To: <20250701141747.00003bf7@huawei.com> References: <20250623152923.1048525-1-fabio.m.de.francesco@linux.intel.com> <20250701141747.00003bf7@huawei.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Tuesday, July 1, 2025 3:17:47=E2=80=AFPM Central European Summer Time Jo= nathan Cameron wrote: > On Mon, 23 Jun 2025 17:29:02 +0200 > "Fabio M. De Francesco" wrote: >=20 > > Add documentation on how to resolve conflicts between CXL Fixed Memory > > Windows, Platform Memory Holes, and Endpoint Decoders. > >=20 > > Signed-off-by: Fabio M. De Francesco > > --- > >=20 > > v2 -> v3: Rework a few phrases for better clarity. > > Fix grammar and syntactic errors (Randy, Alok). > > Fix semantic errors ("size does not comply", Alok). > > Fix technical errors ("decoder's total memory?", Alok). > > =20 > > v1 -> v2: Rewrite "Summary of the Change" section, 3r paragraph. > >=20 > > Documentation/driver-api/cxl/conventions.rst | 85 ++++++++++++++++++++ > > 1 file changed, 85 insertions(+) > >=20 > > diff --git a/Documentation/driver-api/cxl/conventions.rst b/Documentati= on/driver-api/cxl/conventions.rst > > index da347a81a237..d6c8f4cf2f5b 100644 > > --- a/Documentation/driver-api/cxl/conventions.rst > > +++ b/Documentation/driver-api/cxl/conventions.rst > > @@ -45,3 +45,88 @@ Detailed Description of the Change > > ---------------------------------- > > =20 > > > > + > > + > > +Resolve conflict between CFMWS, Platform Memory Holes, and Endpoint De= coders > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D > > + > > +Document > > +-------- > > + > > +CXL Revision 3.2, Version 1.0 > > + > > +License > > +------- > > + > > +SPDX-License Identifier: CC-BY-4.0 > > + > > +Creator/Contributors > > +-------------------- > > + > > +Fabio M. De Francesco, Intel > > +Dan J. Williams, Intel > > +Mahesh Natu, Intel > > + > > +Summary of the Change > > +--------------------- > > + > > +According to the current CXL Specifications (Revision 3.2, Version 1.0) > > +the CXL Fixed Memory Window Structure (CFMWS) describes zero or more H= ost > > +Physical Address (HPA) windows that are associated with each CXL Host > > +Bridge. Each window represents a contiguous HPA range that may be > > +interleaved across one or more targets, some of which are CXL Host Bri= dges. > > +Associated with each window is a set of restrictions that govern its u= sage. > > +It is the OSPM=E2=80=99s responsibility to utilize each window for the= specified > > +use. > > + > > +Table 9-22 states the Window Size field contains the total number of > > +consecutive bytes of HPA this window represents and this value shall b= e a > > +multiple of Number of Interleave Ways * 256 MB. > > + > > +Platform Firmware (BIOS) might reserve part of physical addresses below > > +4 GB (e.g., the Low Memory Hole that describes PCIe memory space for M= MIO > > +or a requirement for the greater than 8 way interleave CXL regions sta= rting > > +at address 0). In that case the Window Size value cannot be anymore > > +constrained to the NIW * 256 MB above-mentioned rule. >=20 > I'm not following argument for large interleave at address 0 being a prob= lem > (if we ignore the low memory hole and similar as a separate issue).=20 > > Even > if it is the interaction with the low memory hole, is 12 way interleave > of 256MiB devices a problem? Fills up to 3GiB.=20 >=20 Right, I'll drop that argument for large interleaves. The problem is still = the=20 MMIO hole that might intersect the 3 GiB requirement for 12 way interleave. Thanks, =46abio