From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D1B8231CA6; Sat, 5 Oct 2024 11:34:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728128064; cv=none; b=R1yxRIsDB/mhT5KWqg8wWXun7KawJyzufgAg/B3ZgtIhZM++VlR+oL3EC/vJ3i334moMg2Qbt35tOrsKW9J3NrSF7lr1Aoj2IENzhf9d+jFt/4P5AbFVxqBf184/yyfe1GP/bDvnh+H/z4L8BGwhv0SL76JvkRiSzqbfbQlSw+4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728128064; c=relaxed/simple; bh=ZqPT3O8DR2o81kxgRM0GY2ztpRihfLRXWZdGTGL6I5o=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=lLaUirHXsaDVkZg19nNOzukjjIoeTkax9eeoNnaMFCeqbbvGqRh6a8dwXtc+5xOTHjzgW+sVcIbs/yjZ06bOMmfYFXKyV+Vw8Dl3uAlVjYbGi84Gsz5+SEdstcd2lNYoa2QDdqZTHUr8IEk6XgLSePonwtZEUfHLz3Fxim0tXKU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TcA50m7u; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TcA50m7u" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84CB1C4CEC2; Sat, 5 Oct 2024 11:34:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1728128063; bh=ZqPT3O8DR2o81kxgRM0GY2ztpRihfLRXWZdGTGL6I5o=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=TcA50m7u0/+IF0HetlMSGIg8779G52V7vcCAy1kMwNgEqGSaXQ2p9LuoCmnyTU7jD fOilEXvtOIIbeNN9azf1tcj52Jp7WzEUC+6KSTllbwV1qQkUjDO0tPt5c673ePC4jH mFq9784yTMQLY8g88BhvZBr1wKNdz8+ICdmbZvMdhIyw2k2DBexjPVCn5XdE7DmmET JU+1dF0XvdAlI+V2MAY+aZKg/YgxxVTxyWI1vCMAe6mvMQ8KVSuwGLV8zWUecX84E0 NatBQamNgPvzWmhKWlDmK+JNexI91UE8tQRhtYjoBtiO4jpnaSuHisN+1FaeyveLMI e8wZ4LzjYWIDw== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sx33F-000aBn-ET; Sat, 05 Oct 2024 12:34:21 +0100 Date: Sat, 05 Oct 2024 12:34:20 +0100 Message-ID: <87iku6vl4z.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v14 3/5] KVM: arm64: Manage GCS access and registers for guests In-Reply-To: <20241005-arm64-gcs-v14-3-59060cd6092b@kernel.org> References: <20241005-arm64-gcs-v14-0-59060cd6092b@kernel.org> <20241005-arm64-gcs-v14-3-59060cd6092b@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 05 Oct 2024 11:37:30 +0100, Mark Brown wrote: > > GCS introduces a number of system registers for EL1 and EL0, on systems > with GCS we need to context switch them and expose them to VMMs to allow > guests to use GCS. > > In order to allow guests to use GCS we also need to configure > HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and > CHKFEAT will report GCS as disabled. Also enable fine grained traps for > access to the GCS registers by guests which do not have the feature > enabled. > > In order to allow userspace to control availability of the feature to > guests we enable writability for only ID_AA64PFR1_EL1.GCS, this is a > deliberately conservative choice to avoid errors due to oversights. > Further fields should be made writable in future. It appears I have accidentally dropped the branch fixing ID_AA64PFR1_EL1. I'll make sure this goes in as quickly as possible. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++ > arch/arm64/include/asm/vncr_mapping.h | 2 ++ > arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++++++ > arch/arm64/kvm/sys_regs.c | 31 +++++++++++++++++++++++++++++- > 4 files changed, 75 insertions(+), 1 deletion(-) > [...] > @@ -4716,6 +4737,14 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) > kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 | > HFGxTR_EL2_nPOR_EL0); > > + if (!kvm_has_gcs(kvm)) { > + kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nGCS_EL0 | > + HFGxTR_EL2_nGCS_EL1); > + kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_nGCSEPP | > + HFGITR_EL2_nGCSSTR_EL1 | > + HFGITR_EL2_nGCSPUSHM_EL1); Where is the handling of traps resulting of HFGITR_EL2.nGCSSTR_EL1? M. -- Without deviation from the norm, progress is not possible.