From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38F9C2B9BE; Sun, 2 Jun 2024 13:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717336385; cv=none; b=a3a0IPGrcEJbcfBcZHaZ9rclXl5nvxOjk1WOS/RVOvKpTK+RptOp8d2mmCUTY2cHWEB9tIexjJzTbDFmctNUr6GVBFQZjIuLN2EIg2Si3FCpyprNNRQbuc+lw/13xchnCaGBW4ALNRcP5lO3H/kFyFzwHYXImfgW0moHqNtTp6c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717336385; c=relaxed/simple; bh=DeL5aeSA5tvcVCR2KVHhivWXgJ21YbHHOT6rNYrcTrw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=m2UZBVlXpAU5NLCP9Db9gnxW3OhDurnK07D3y5bzCTclBzqTtfTlxP30f8+IapRknHuN1Q41rCcWvesojVQSO023EQ7Pc47+UjC4u4KixBWBCxy9tiMByLccpC4M3y1z/AeaYgfT9efi6sFm98FmC8Fzp+XoH8P0j3GtFI5Js8c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ppHRVVz+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ppHRVVz+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A19C5C2BBFC; Sun, 2 Jun 2024 13:53:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717336384; bh=DeL5aeSA5tvcVCR2KVHhivWXgJ21YbHHOT6rNYrcTrw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ppHRVVz+0PtvG8TMK054YMKaO989L5de2R+5klqf3WnUm6UADjkIf4HPjx7DigvI1 uLCe934prVquN6n8DGXkBdvh6kfbmDyFiwdv2RmFDIHn/RuQ/PBXmNbkAcp0Vtt41a iS2UzoTJhHhVScZEKY028TSq82FGtZzR1k4dZjgNkJRmNy8cUWWTw30KFsGw71LTfH kr1bc2fSButlekEwjT0eig4PL+WJL24SxAwwZbxNgAxr11pk/jxC3A4Dj55ocC7Vwa wlY1wjmmyk3ojnOty1ONIOJjbOHAzaHheR/8k1O6mBrSm9yn2UisoEccEoFx+L5x/Z TgBVXbFTQPRsw== Received: from sofa.misterjones.org ([185.219.108.64] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sDldu-00HZRE-3k; Sun, 02 Jun 2024 14:53:02 +0100 Date: Sun, 02 Jun 2024 14:53:02 +0100 Message-ID: <87ikyr30zl.wl-maz@kernel.org> From: Marc Zyngier To: yu harry Cc: corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] irqchip/gic-v3: Add Allwinner sunxi001 erratum workaround In-Reply-To: References: <20240602071058.6405-1-harry.yu185@gmail.com> <86o78jlms2.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: harry.yu185@gmail.com, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, tglx@linutronix.de, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sun, 02 Jun 2024 14:23:43 +0100, yu harry wrote: >=20 > On Sun, Jun 2, 2024 at 5:25=E2=80=AFPM Marc Zyngier wrot= e: > > > > On Sun, 02 Jun 2024 08:10:58 +0100, > > "harry.yu185" wrote: > > > > > > Allwinner A523 GIC600 integration does not support the > > > sharability feature. So assigned Erratum ID #sunxi001 for this > > > issue. > > > > > > That the 0x0201643b ID is not Allwinner specific and thus > > > there is an extra of_machine_is_compatible() check. > > > > > > Note, because more than one soc may have this problem, the 'sunxi' > > > name is used instead of a fixed soc name like A523. > > > > > > Signed-off-by: harry.yu185 > > > > No, this is all already handled by the driver already (since 6.6). > > > > Please fix your DT to include the "dma-noncoherent" property in the > > GIC and ITS nodes, which should paper over the integration bug. > > > > Thanks, > > > > M. > > > > -- > > Without deviation from the norm, progress is not possible. >=20 > Thank you for your reply, > the method you said may not be suitable, because this SOC > also needs RDIST_FLAGS_FORCE_NON_SHAREABLE, > just like RK3588, but it is different from the RK3588 version. Who is talking of RK3588? Have you read what I wrote? Have you actually looked at what these attributes do? For context, here's what you're proposing: +static bool __maybe_unused its_enable_sunxi001(void *data) +{ + struct its_node *its =3D data; + + if (!of_machine_is_compatible("arm,sun55iw3p1")) + return false; + + its->flags |=3D ITS_FLAGS_FORCE_NON_SHAREABLE; + gic_rdists->flags |=3D RDIST_FLAGS_FORCE_NON_SHAREABLE; + + return true; +} + "dma-noncoherent" on the GIC node provides: static bool rd_set_non_coherent(void *data) { struct gic_chip_data *d =3D data; d->rdists.flags |=3D RDIST_FLAGS_FORCE_NON_SHAREABLE; return true; } "dma-noncoherent" on the ITS node provides: static bool its_set_non_coherent(void *data) { struct its_node *its =3D data; its->flags |=3D ITS_FLAGS_FORCE_NON_SHAREABLE; return true; } So please do explain how the combination of the two isn't equivalent to your patch. How does it fail to provide the required workaround? M. --=20 Without deviation from the norm, progress is not possible.