From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B3461442FC; Sun, 31 Mar 2024 10:59:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711882750; cv=none; b=mE2QJmQaRFWpC77Zk86KzIytnIw+PmbOrvlk8N3YcLk+c+XNgsDunycRo7j5IFeg0w9AMT5OUVcdupkwW0KBWhCHtolZ+3Xs8hUY8ywR6awgCCx3CHjRvD/6z1M7luaVmNaDWqJxYexsNdHABCo7ZWIZ5P4liaLj9Ct522UZDWY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711882750; c=relaxed/simple; bh=E/mXO2r8N+mvHUjPMnvWB+Izzfu4L00THFiMK03lb68=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=unv5mOchm02l9EyaJgtpkb1SQA+F1m49zkocsKnJM5Y6EbCIW+wr6nAI1riJZwPNnO16iCP4qcQoXykclYVMnlaxWGWkrGEXq2H8QLzeN8VswQZLMv1i852ptQ4Iq+QGNpfXiWno2o9ZHFe8i40oAFi8ypqjsMOgBBjKBHnTcXw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ERqxj6v8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ERqxj6v8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B61FCC433F1; Sun, 31 Mar 2024 10:59:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711882749; bh=E/mXO2r8N+mvHUjPMnvWB+Izzfu4L00THFiMK03lb68=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ERqxj6v8X0bw8+Nn+UE7aUiWGYJc9LvPo4mBhsECJoHarVZLp3LXI7/62lAKBZap3 GNdoJwAn6Q2oj9ABUEihq76OhmeRXXlifkDzaOieupHDMIgPrf6Nh0A1yBmWwQhBUn l2TjZW042YsgfyPN3wsh67WXvdLDSaIbF4tbVvMmFyPYjA2J4Rjv1Z9u8MqZPvJ1Lx iXuxOEjcbKO7F0h9mPEkG0ZtiMjbDBHzWcgFSzszSNJjsVo/HB9broW2NE45amyl4q Bh86kTlGq1jzIVKVFrodRfdnMv/V+mojH0BBsljrTxB1MEXkQYlFPXTj/wTPVyAUEl 9+eBc973iZJyQ== Received: from 82-132-233-13.dab.02.net ([82.132.233.13] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rqsu3-0001gL-Ea; Sun, 31 Mar 2024 11:59:07 +0100 Date: Sun, 31 Mar 2024 11:59:06 +0100 Message-ID: <87le5ysm4l.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v6 2/5] KVM: arm64: Add newly allocated ID registers to register descriptions In-Reply-To: <20240329-arm64-2023-dpisa-v6-2-ba42db6c27f3@kernel.org> References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> <20240329-arm64-2023-dpisa-v6-2-ba42db6c27f3@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 82.132.233.13 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, corbet@lwn.net, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave.Martin@arm.com, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 29 Mar 2024 00:13:43 +0000, Mark Brown wrote: > > The 2023 architecture extensions have allocated some new ID registers, add > them to the KVM system register descriptions so that they are visible to > guests. > > We make the newly introduced dpISA features writeable, as well as > allowing writes to ID_AA64ISAR3_EL1.CPA for FEAT_CPA which only > introduces straigforward new instructions with no additional > architectural state or traps. FPMR actively gets trapped by HCRX_EL2. > > Signed-off-by: Mark Brown > --- > arch/arm64/kvm/sys_regs.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index c9f4f387155f..a3c20d1a36aa 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -2293,12 +2293,15 @@ static const struct sys_reg_desc sys_reg_descs[] = { > ID_AA64PFR0_EL1_AdvSIMD | > ID_AA64PFR0_EL1_FP), }, > ID_SANITISED(ID_AA64PFR1_EL1), > - ID_UNALLOCATED(4,2), > + ID_WRITABLE(ID_AA64PFR2_EL1, ~(ID_AA64PFR2_EL1_RES0 | > + ID_AA64PFR2_EL1_MTEFAR | > + ID_AA64PFR2_EL1_MTESTOREONLY | > + ID_AA64PFR2_EL1_MTEPERM)), > ID_UNALLOCATED(4,3), > ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), > ID_HIDDEN(ID_AA64SMFR0_EL1), > ID_UNALLOCATED(4,6), > - ID_UNALLOCATED(4,7), > + ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), > > /* CRm=5 */ > { SYS_DESC(SYS_ID_AA64DFR0_EL1), > @@ -2325,7 +2328,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { > ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | > ID_AA64ISAR2_EL1_APA3 | > ID_AA64ISAR2_EL1_GPA3)), > - ID_UNALLOCATED(6,3), > + ID_WRITABLE(ID_AA64ISAR3_EL1, ~(ID_AA64ISAR2_EL1_RES0 | > + ID_AA64ISAR3_EL1_PACM | > + ID_AA64ISAR3_EL1_TLBIW)), > ID_UNALLOCATED(6,4), > ID_UNALLOCATED(6,5), > ID_UNALLOCATED(6,6), > Where is the code that enforces the lack of support for MTEFAR, MTESTOREONLY, and MTEPERM for SCTLR_ELx, EnPACM and EnFPM in HCRX_EL2? And I haven't checked whether TLBI VMALLWS2 can be trapped. M. -- Without deviation from the norm, progress is not possible.