From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Takahiro Kuwano <takahiro.kuwano@infineon.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Sean Anderson <sean.anderson@linux.dev>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Steam Lin <STLin2@winbond.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, stable@kernel.org
Subject: Re: [PATCH v5 04/28] mtd: spi-nor: swp: Improve locking user experience
Date: Fri, 22 May 2026 18:39:52 +0200 [thread overview]
Message-ID: <87o6i7o0tj.fsf@bootlin.com> (raw)
In-Reply-To: <779f2680-2c67-4bbd-9576-bde8e83d111d@linaro.org> (Tudor Ambarus's message of "Fri, 22 May 2026 19:07:53 +0300")
>> Technically speaking all four first patches are fixes, except I don't
>> ask the first one to be backported. The reason why we ask fixes to be
>> first in the series is because we want them to be as independent as
>> possible from previous cleanups/changes. Here each four first patch are
>> targeting completely different places and should not interact with each
>> other. Anyway, I will re-shuffle the patches.
>
> you don't need to resend just for that I think. Pratyush or Michael can
> re-shuffle when applying.
It's a bit painful to do while applying, I will send a v6.
>> As for Sashiko's feedback, the AI raises the same point as our previous
>> discussion: the QE bit handling is really bad, and I am working on
>
> I forgot what we talked about, sorry.
The fact that there is a helper in the core that blindly sets a
particular QE bit, but this helper might (theoretically) be used by
chips which have the QE bit somewhere else.
I plan on reworking this by storing the location of the QE bit during
SFDP parsing. Then I will use that location in a helper to set or clear
it, which will also be dependent on the QER bitfield. But that field is
a real mess, so I'm not sure it's gonna work :-)
Cheers,
Miquèl
next prev parent reply other threads:[~2026-05-22 16:39 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 16:46 [PATCH v5 00/28] mtd: spi-nor: Enhance software protection Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 01/28] mtd: spi-nor: Drop duplicate Kconfig dependency Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 02/28] mtd: spi-nor: debugfs: Fix the flags list Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 03/28] mtd: spi-nor: Make sure the QE bit is kept enabled if useful Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 04/28] mtd: spi-nor: swp: Improve locking user experience Miquel Raynal
2026-05-22 9:10 ` Tudor Ambarus
2026-05-22 15:55 ` Miquel Raynal
2026-05-22 16:07 ` Tudor Ambarus
2026-05-22 16:39 ` Miquel Raynal [this message]
2026-05-07 16:46 ` [PATCH v5 05/28] mtd: spi-nor: Improve opcodes documentation Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 06/28] mtd: spi-nor: debugfs: Align variable access with the rest of the file Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 07/28] mtd: spi-nor: debugfs: Enhance output Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 08/28] mtd: spi-nor: swp: Explain the MEMLOCK ioctl implementation behaviour Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 09/28] mtd: spi-nor: swp: Clarify a comment Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 10/28] mtd: spi-nor: swp: Use a pointer for SR instead of a single byte Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 11/28] mtd: spi-nor: swp: Create a helper that writes SR, CR and checks Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 12/28] mtd: spi-nor: swp: Rename a mask Miquel Raynal
2026-05-22 9:37 ` Tudor Ambarus
2026-05-07 16:46 ` [PATCH v5 13/28] mtd: spi-nor: swp: Create a TB intermediate variable Miquel Raynal
2026-05-22 9:39 ` Tudor Ambarus
2026-05-22 16:06 ` Miquel Raynal
2026-05-22 16:19 ` Tudor Ambarus
2026-05-07 16:46 ` [PATCH v5 14/28] mtd: spi-nor: swp: Create helpers for building the SR register Miquel Raynal
2026-05-22 9:56 ` Tudor Ambarus
2026-05-22 16:35 ` Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 15/28] mtd: spi-nor: swp: Simplify checking the locked/unlocked range Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 16/28] mtd: spi-nor: swp: Cosmetic changes Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 17/28] mtd: spi-nor: Create a local SR cache Miquel Raynal
2026-05-07 16:46 ` [PATCH v5 18/28] mtd: spi-nor: debugfs: Add locking support Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 19/28] mtd: spi-nor: debugfs: Add a locked sectors map Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 20/28] mtd: spi-nor: Add steps for testing locking support Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 21/28] mtd: spi-nor: swp: Add support for the complement feature Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 22/28] mtd: spi-nor: Add steps for testing locking with CMP Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 23/28] mtd: spi-nor: winbond: Add W25H512NWxxAM CMP locking support Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 24/28] mtd: spi-nor: winbond: Add W25H01NWxxAM " Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 25/28] mtd: spi-nor: winbond: Add W25H02NWxxAM " Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 26/28] mtd: spi-nor: winbond: Add W25H01NWxxIQ " Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 27/28] mtd: spi-nor: winbond: Add W25Q01NWxxIM " Miquel Raynal
2026-05-07 16:47 ` [PATCH v5 28/28] mtd: spi-nor: winbond: Add W25Q02NWxxIM " Miquel Raynal
2026-05-22 9:07 ` [PATCH v5 00/28] mtd: spi-nor: Enhance software protection Tudor Ambarus
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