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From: Marc Zyngier <maz@kernel.org>
To: Marek Vasut <marek.vasut@mailbox.org>
Cc: "Manivannan Sadhasivam" <mani@kernel.org>,
	linux-pci@vger.kernel.org,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v4 0/5] PCI: rcar-gen4: irqchip/gic-v3: Handle GIC ITS
Date: Thu, 09 Jul 2026 13:43:26 +0100	[thread overview]
Message-ID: <87v7ao5o5t.wl-maz@kernel.org> (raw)
In-Reply-To: <c12941e4-3715-404e-b674-090c62b868b8@mailbox.org>

On Thu, 09 Jul 2026 13:33:22 +0100,
Marek Vasut <marek.vasut@mailbox.org> wrote:
> 
> On 7/9/26 2:19 PM, Manivannan Sadhasivam wrote:
> > On Tue, Jul 07, 2026 at 10:35:38PM +0200, Marek Vasut wrote:
> >> Configure all R-Car Gen4 PCIe controller MSI registers fully, both in
> >> case MSI are enabled and disabled.
> >> 
> >> Patch GIC ITS driver and add quirks for R-Car Gen4 GIC ITS, which is
> >> configured to 32-bit address width for AXI or APB interface.
> >> 
> >> Switch R-Car V4H to use GIC ITS in its DT and describe the GIC ITS
> >> implementation cacheable and shareable limitations.
> >> 
> >> Marek Vasut (5):
> >>    PCI: dwc: Determine whether iMSI is used before calling .init
> >>    PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used
> >>    irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling
> >>    irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround
> > 
> > Is there a functional dependency between irqchip and PCI patches? Since the
> > irqchip patches touch ARM64 Kconfig etc... I'm wondering if it still need to go
> > through PCI tree.
> I do not believe there is.
> 
> These two configure the PCIe controller hardware:
>   PCI: dwc: Determine whether iMSI is used before calling .init
>   PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used
> 
> These two fill in GIC ITS quirks:
>   irqchip/gic-v3: Refactor GIC600 limited to 32bit PA erratum handling
>   irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround
> 
> This one does yes depend on the two and two patches above, and can
> only be applied once all four aforementioned patches land, otherwise
> things really yes will break:
>   arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes
> 
> Would you like me to split the series up , or can you and Marc (?)
> pick the relevant parts via matching trees ?

I don't think there's anything for me to pick. The whole thing looks
like a consistent set, and it probably should be kept together.

Given that the irqchip stuff has been acked by the relevant party, and
that the last patch will cause havoc if taken on its own, the only
course of action is to route the whole thing together, the PCI tree
being the most obvious victim.

	M.

-- 
Jazz isn't dead. It just smells funny.

  parent reply	other threads:[~2026-07-09 12:41 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-07 20:35 [PATCH v4 0/5] PCI: rcar-gen4: irqchip/gic-v3: Handle GIC ITS Marek Vasut
2026-07-07 20:35 ` [PATCH v4 1/5] PCI: dwc: Determine whether iMSI is used before calling .init Marek Vasut
2026-07-07 20:35 ` [PATCH v4 2/5] PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used Marek Vasut
2026-07-07 20:35 ` [PATCH v4 4/5] irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround Marek Vasut
2026-07-07 20:35 ` [PATCH v4 5/5] arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes Marek Vasut
2026-07-09 12:19 ` [PATCH v4 0/5] PCI: rcar-gen4: irqchip/gic-v3: Handle GIC ITS Manivannan Sadhasivam
2026-07-09 12:33   ` Marek Vasut
2026-07-09 12:41     ` Manivannan Sadhasivam
2026-07-09 12:43     ` Marc Zyngier [this message]
2026-07-09 12:57       ` Manivannan Sadhasivam
2026-07-09 15:22         ` Marek Vasut
2026-07-09 12:57 ` (subset) " Manivannan Sadhasivam
2026-07-09 12:59   ` Manivannan Sadhasivam
2026-07-09 15:23     ` Marek Vasut

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