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([2600:8803:e7e4:1d00:96a3:e28:3f6:dbac]) by smtp.gmail.com with ESMTPSA id 5614622812f47-401ec8cb1ebsm971268b6e.18.2025.04.25.15.50.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Apr 2025 15:51:00 -0700 (PDT) Message-ID: <88a326e7-3910-4e02-b4ba-7afe06402871@baylibre.com> Date: Fri, 25 Apr 2025 17:50:58 -0500 Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] dt-bindings: iio: adc: Add adi,ad4052 To: Jorge Marques , Jonathan Cameron , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-pwm@vger.kernel.org References: <20250422-iio-driver-ad4052-v2-0-638af47e9eb3@analog.com> <20250422-iio-driver-ad4052-v2-3-638af47e9eb3@analog.com> From: David Lechner Content-Language: en-US In-Reply-To: <20250422-iio-driver-ad4052-v2-3-638af47e9eb3@analog.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 4/22/25 6:34 AM, Jorge Marques wrote: > Add dt-bindings for AD4052 family, devices AD4050/AD4052/AD4056/AD4058, > low-power with monitor capabilities SAR ADCs. > Each variant of the family differs in speed and resolution, resulting > in different scan types and spi word sizes, that are matched by the > compatible with the chip_info. > The device contains one input (cnv) and two outputs (gp0, gp1). Don't need line breaks after every period. > > Signed-off-by: Jorge Marques > --- ... > + interrupts: > + items: > + - description: Signal coming from the GP0 pin (threshold). > + - description: Signal coming from the GP1 pin (data ready). > + > + interrupt-names: > + items: > + - const: gp0 > + - const: gp1 > + > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 > + description: | > + The first cell is the GPn number: 0 to 1. > + The second cell takes standard GPIO flags. > + > + cnv-gpios: > + description: The Convert Input (CNV). If omitted, CNV is tied to SPI CS. > + maxItems: 1 > + Assuming the diagram at [1] is correct, for SPI offload use, we are missing: #trigger-source-cells: const: 2 description: | Output pins used as trigger source. Cell 0 defines which pin: * 0 = GP0 * 1 = GP1 Cell 1 defines the event: * 0 = Data ready * 1 = Min threshold * 2 = Max threshold * 3 = Either threshold * 4 = Device ready * 5 = Device enable * 6 = Chop control Bonus points for adding a header with macros for the arbitrary event values. And we are missing: pwms: maxItems: 1 description: PWM connected to the CNV pin. [1]: https://analogdevicesinc.github.io/hdl/projects/ad4052_ardz/index.html > + spi-max-frequency: > + maximum: 62500000 Datasheet Table 5. SPI Timing—ADC Modes, VIO ≥ 3.0 V says period can be 12 ns. So that would make max frequency 83333333. ... > +examples: > + - | > + #include > + #include > + > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + > + adc@0 { > + compatible = "adi,ad4052"; > + reg = <0>; > + vdd-supply = <&adc_vdd>; > + vio-supply = <&adc_vio>; > + spi-max-frequency = <25000000>; > + > + interrupt-parent = <&gpio>; > + interrupts = <0 0 IRQ_TYPE_EDGE_RISING>, > + <0 1 IRQ_TYPE_EDGE_FALLING>; > + interrupt-names = "gp0", "gp1"; > + cnv-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; > + }; > + }; Could be nice to have a 2nd example showing SPI offload usage.