[PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Nuno Sá via B4 Relay]

This is v3 for the LTC4283 how swap controller. Main change is that I'm
now using the auxiliary bus for adding the GPIO device (done depending
on FW properties).

Similar to the LTC4282 device, we're clearing some fault logs in the
reset_history attributes.

Guenter, in [1] you can find some replies for some questions you had in
v2 that likely you don't remember anymore. Regarding the regmap story I
ended up adding a secong regmap for the 16 bit wide registers which
seems like a clean solution (if I'm not missing nothing).

[1]: https://lore.kernel.org/linux-hwmon/0765a0b89779331c62a3f136ef030f7f2f40ea47.camel@gmail.com/
[2]: https://lore.kernel.org/linux-iio/cover.1761588465.git.geert+renesas@glider.be/

---
Changes in v5:
- Patch 2:
  * Added a secong regmap for the 16bit wide registers;
  * Add default value for rsense so that we can probe without FW
    properties;
  * Make sure to give the right file permissions to the reset_history
    attrs.
- Patch 3:
  * Make sure to get the right regmap (given that the device now has 2);
  * Add error handling for getting the regmap.
- Link to v4: https://lore.kernel.org/r/20251204-ltc4283-support-v4-0-db0197fd7984@analog.com

---
Nuno Sá (3):
      dt-bindings: hwmon: Document the LTC4283 Swap Controller
      hwmon: ltc4283: Add support for the LTC4283 Swap Controller
      gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller

 .../devicetree/bindings/hwmon/adi,ltc4283.yaml     |  272 +++
 Documentation/hwmon/index.rst                      |    1 +
 Documentation/hwmon/ltc4283.rst                    |  266 +++
 MAINTAINERS                                        |    9 +
 drivers/gpio/Kconfig                               |   15 +
 drivers/gpio/Makefile                              |    1 +
 drivers/gpio/gpio-ltc4283.c                        |  218 +++
 drivers/hwmon/Kconfig                              |   12 +
 drivers/hwmon/Makefile                             |    1 +
 drivers/hwmon/ltc4283.c                            | 1766 ++++++++++++++++++++
 10 files changed, 2561 insertions(+)
---
base-commit: bc04acf4aeca588496124a6cf54bfce3db327039
change-id: 20250812-ltc4283-support-27c8c4e69c6b
--

Thanks!
- Nuno Sá

[PATCH v5 1/3] dt-bindings: hwmon: Document the LTC4283 Swap Controller

[Nuno Sá via B4 Relay]

From: Nuno Sá <nuno.sa@analog.com>

The LTC4283 is a negative voltage hot swap controller that drives an
external N-channel MOSFET to allow a board to be safely inserted and
removed from a live backplane.

Special note for the "adi,vpower-drns-enable" property. It allows to choose
between the attenuated MOSFET drain voltage or the attenuated input
voltage at the RTNS pin (effectively choosing between input or output
power). This is a system level decision not really intended to change at
runtime and hence is being added as a Firmware property.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
 .../devicetree/bindings/hwmon/adi,ltc4283.yaml     | 272 +++++++++++++++++++++
 MAINTAINERS                                        |   6 +
 2 files changed, 278 insertions(+)

diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml
new file mode 100644
index 000000000000..f82fff1ec7e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml
@@ -0,0 +1,272 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/adi,ltc4283.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LTC4283 Negative Voltage Hot Swap Controller
+
+maintainers:
+  - Nuno Sá <nuno.sa@analog.com>
+
+description: |
+  The LTC4283 negative voltage hot swap controller drives an external N-channel
+  MOSFET to allow a board to be safely inserted and removed from a live
+  backplane.
+
+  https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4283.pdf
+
+properties:
+  compatible:
+    enum:
+      - adi,ltc4283
+
+  reg:
+    maxItems: 1
+
+  adi,rsense-nano-ohms:
+    description: Value of the sense resistor.
+
+  adi,current-limit-sense-microvolt:
+    description:
+      The current limit sense voltage of the chip is adjustable between
+      15mV and 30mV in 1mV steps. This effectively limits the current
+      on the load.
+    minimum: 15000
+    maximum: 30000
+    default: 15000
+
+  adi,current-limit-foldback-factor:
+    description:
+      Specifies the foldback factor for the current limit. The current limit
+      can be reduced (folded back) to one of four preset levels. The value
+      represents the percentage of the current limit sense voltage to use
+      during foldback. A value of 100 means no foldback.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [10, 20, 50, 100]
+    default: 100
+
+  adi,cooling-delay-ms:
+    description:
+      Cooling time to apply after an overcurrent fault, FET bad or
+      external fault.
+    enum: [512, 1002, 2005, 4100, 8190, 16400, 32800, 65600]
+    default: 512
+
+  adi,fet-bad-timer-delay-ms:
+    description:
+      FET bad timer delay. After a FET bad status condition is detected,
+      this timer is started. If the condition persists for the
+      specified time, the FET is turned off and a fault is logged.
+    enum: [256, 512, 1002, 2005]
+    default: 256
+
+  adi,power-good-reset-on-fet:
+    description:
+      If set, resets the power good status when the MOSFET is turned off.
+      Otherwise, it resets when a low output voltage is detected.
+    type: boolean
+
+  adi,fet-turn-off-disable:
+    description:
+      If set, the MOSFET is turned off immediately when a FET fault is detected.
+    type: boolean
+
+  adi,tmr-pull-down-disable:
+    description: Disables 2uA pull-down current on the TMR pin.
+    type: boolean
+
+  adi,dvdt-inrush-control-disable:
+    description:
+      Enables dV/dt inrush control during startup. In dV/dt mode, the inrush
+      current is limited by controlling a constant output voltage ramp rate.
+      If not set, the inrush control mechanism is active current limiting.
+    type: boolean
+
+  adi,fault-log-enable:
+    description:
+      If set, enables logging fault registers and ADC data into EEPROM upon a
+      fault.
+    type: boolean
+
+  adi,vpower-drns-enable:
+    description:
+      If set, enables the attenuated MOSFET drain voltage to be monitored. This
+      effectively means that the MOSFET power is monitored. If not set, the
+      attenuated input voltage (and hence input power) is monitored.
+    type: boolean
+
+  adi,external-fault-fet-off-enable:
+    description: Turns MOSFET off following an external fault.
+    type: boolean
+
+  adi,undervoltage-retry-disable:
+    description: Do not retry to turn on the MOSFET after an undervoltage fault.
+    type: boolean
+
+  adi,overvoltage-retry-disable:
+    description: Do not retry to turn on the MOSFET after an overvoltage fault.
+    type: boolean
+
+  adi,external-fault-retry-enable:
+    description: Retry to turn on the MOSFET retry after an external fault.
+    type: boolean
+
+  adi,overcurrent-retries:
+    description: Configures auto-retry following an Overcurrent fault.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [latch-off, "1", "7", unlimited]
+    default: latch-off
+
+  adi,fet-bad-retries:
+    description:
+      Configures auto-retry following a FET bad fault and a consequent MOSFET
+      turn off.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [latch-off, "1", "7", unlimited]
+    default: latch-off
+
+  adi,pgio1-func:
+    description: Configures the function of the PGIO1 pin.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [inverted_power_good, power_good, gpio]
+    default: inverted_power_good
+
+  adi,pgio2-func:
+    description: Configures the function of the PGIO2 pin.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [inverted_power_good, power_good, gpio, active_current_limiting]
+    default: inverted_power_good
+
+  adi,pgio3-func:
+    description: Configures the function of the PGIO3 pin.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [inverted_power_good_input, power_good_input, gpio]
+    default: inverted_power_good_input
+
+  adi,pgio4-func:
+    description: Configures the function of the PGIO4 pin.
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [inverted_external_fault, external_fault, gpio]
+    default: inverted_external_fault
+
+  adi,gpio-on-adio1:
+    description: If set, the ADIO1 pin is used as a GPIO.
+    type: boolean
+
+  adi,gpio-on-adio2:
+    description: If set, the ADIO2 pin is used as a GPIO.
+    type: boolean
+
+  adi,gpio-on-adio3:
+    description: If set, the ADIO3 pin is used as a GPIO.
+    type: boolean
+
+  adi,gpio-on-adio4:
+    description: If set, the ADIO4 pin is used as a GPIO.
+    type: boolean
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+dependencies:
+  adi,gpio-on-adio1:
+    - gpio-controller
+    - '#gpio-cells'
+  adi,gpio-on-adio2:
+    - gpio-controller
+    - '#gpio-cells'
+  adi,gpio-on-adio3:
+    - gpio-controller
+    - '#gpio-cells'
+  adi,gpio-on-adio4:
+    - gpio-controller
+    - '#gpio-cells'
+  adi,external-fault-retry-enable:
+    - adi,pgio4-func
+  adi,external-fault-fet-off-enable:
+    - adi,pgio4-func
+
+required:
+  - compatible
+  - reg
+  - adi,rsense-nano-ohms
+
+allOf:
+  - if:
+      properties:
+        adi,pgio1-func:
+          const: gpio
+      required:
+        - adi,pgio1-func
+    then:
+      required:
+        - gpio-controller
+        - '#gpio-cells'
+
+  - if:
+      properties:
+        adi,pgio2-func:
+          const: gpio
+      required:
+        - adi,pgio2-func
+    then:
+      required:
+        - gpio-controller
+        - '#gpio-cells'
+
+  - if:
+      properties:
+        adi,pgio3-func:
+          const: gpio
+      required:
+        - adi,pgio3-func
+    then:
+      required:
+        - gpio-controller
+        - '#gpio-cells'
+
+  - if:
+      properties:
+        adi,pgio4-func:
+          const: gpio
+      required:
+        - adi,pgio4-func
+    then:
+      properties:
+        adi,external-fault-retry-enable: false
+        adi,external-fault-fet-off-enable: false
+      required:
+        - gpio-controller
+        - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        swap-controller@15 {
+            compatible = "adi,ltc4283";
+            reg = <0x15>;
+
+            adi,rsense-nano-ohms = <500>;
+            adi,current-limit-sense-microvolt = <25000>;
+            adi,current-limit-foldback-factor = <10>;
+            adi,cooling-delay-ms = <8190>;
+            adi,fet-bad-timer-delay-ms = <512>;
+
+            adi,external-fault-fet-off-enable;
+            adi,pgio4-func = "external_fault";
+
+            adi,gpio-on-adio1;
+            adi,pgio1-func = "gpio";
+            gpio-controller;
+            #gpio-cells = <2>;
+        };
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index ea364af99ba5..b52fc2c777dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14955,6 +14955,12 @@ F:	Documentation/devicetree/bindings/hwmon/adi,ltc4282.yaml
 F:	Documentation/hwmon/ltc4282.rst
 F:	drivers/hwmon/ltc4282.c
 
+LTC4283 HARDWARE MONITOR AND GPIO DRIVER
+M:	Nuno Sá <nuno.sa@analog.com>
+L:	linux-hwmon@vger.kernel.org
+S:	Supported
+F:	Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml
+
 LTC4286 HARDWARE MONITOR DRIVER
 M:	Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com>
 L:	linux-hwmon@vger.kernel.org

-- 
2.52.0

[PATCH v5 2/3] hwmon: ltc4283: Add support for the LTC4283 Swap Controller

[Nuno Sá via B4 Relay]

From: Nuno Sá <nuno.sa@analog.com>

Support the LTC4283 How Swap Controller. The device features programmable
current limit with foldback and independently adjustable inrush current to
optimize the MOSFET safe operating area (SOA). The SOA timer limits MOSFET
temperature rise for reliable protection against overstresses.

An I2C interface and onboard ADC allow monitoring of board current,
voltage, power, energy, and fault status.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
 Documentation/hwmon/index.rst   |    1 +
 Documentation/hwmon/ltc4283.rst |  266 ++++++
 MAINTAINERS                     |    1 +
 drivers/hwmon/Kconfig           |   12 +
 drivers/hwmon/Makefile          |    1 +
 drivers/hwmon/ltc4283.c         | 1766 +++++++++++++++++++++++++++++++++++++++
 6 files changed, 2047 insertions(+)

diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 85d7a686883e..dc4080d40def 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -143,6 +143,7 @@ Hardware Monitoring Kernel Drivers
    ltc4260
    ltc4261
    ltc4282
+   ltc4283
    ltc4286
    macsmc-hwmon
    max127
diff --git a/Documentation/hwmon/ltc4283.rst b/Documentation/hwmon/ltc4283.rst
new file mode 100644
index 000000000000..0a8d72904122
--- /dev/null
+++ b/Documentation/hwmon/ltc4283.rst
@@ -0,0 +1,266 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+
+Kernel drivers ltc4283
+==========================================
+
+Supported chips:
+
+  * Analog Devices LTC4283
+
+    Prefix: 'ltc4283'
+
+    Addresses scanned: - I2C 0x10 - 0x17 (7-bit)
+    Addresses scanned: - I2C 0x20 - 0x2E (8-bit)
+
+    Datasheet:
+
+        https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4283.pdf
+
+Author: Nuno Sá <nuno.sa@analog.com>
+
+Description
+___________
+
+The LTC4283 negative voltage hot swap controller drives an external N-channel
+MOSFET to allow a board to be safely inserted and removed from a live backplane.
+The device features programmable current limit with foldback and independently
+adjustable inrush current to optimize the MOSFET safe operating area (SOA). The
+SOA timer limits MOSFET temperature rise for reliable protection against
+overstresses. An I2C interface and onboard gear-shift ADC allow monitoring of
+board current, voltage, power, energy, and fault status.  Additional features
+respond to input UV/OV, interrupt the host when a fault has occurred, notify
+when output power is good, detect insertion of a board, turn off the MOSFET
+if an external supply monitor fails to indicate power good within a timeout
+period, and auto-reboot after a programmable delay following a host commanded
+turn-off.
+
+Sysfs entries
+_____________
+
+The following attributes are supported. Limits are read-write and all the other
+attributes are read-only. Note that the VADIOx channels might not be available
+if the ADIO pins are used as GPIOs (naturally also affects the respective
+differential channels).
+
+======================= ==========================================
+in0_lcrit_alarm         Critical Undervoltage alarm
+in0_crit_alarm          Critical Overvoltage alarm
+in0_label		Channel label (VIN)
+
+in1_input		Output voltage (mV).
+in1_min			Undervoltage threshold
+in1_max			Overvoltage threshold
+in1_lowest		Lowest measured voltage
+in1_highest		Highest measured voltage
+in1_reset_history	Write 1 to reset history.
+in1_min_alarm		Undervoltage alarm
+in1_max_alarm		Overvoltage alarm
+in1_label		Channel label (VPWR)
+
+in2_input		Output voltage (mV).
+in2_min			Undervoltage threshold
+in2_max			Overvoltage threshold
+in2_lowest		Lowest measured voltage
+in2_highest		Highest measured voltage
+in2_reset_history	Write 1 to reset history.
+in2_min_alarm		Undervoltage alarm
+in2_max_alarm		Overvoltage alarm
+in2_enable		Enable/Disable monitoring.
+in2_label		Channel label (VADI1)
+
+in3_input		Output voltage (mV).
+in3_min			Undervoltage threshold
+in3_max			Overvoltage threshold
+in3_lowest		Lowest measured voltage
+in3_highest		Highest measured voltage
+in3_reset_history	Write 1 to reset history.
+in3_min_alarm		Undervoltage alarm
+in3_max_alarm		Overvoltage alarm
+in3_enable		Enable/Disable monitoring.
+in3_label		Channel label (VADI2)
+
+in4_input		Output voltage (mV).
+in4_min			Undervoltage threshold
+in4_max			Overvoltage threshold
+in4_lowest		Lowest measured voltage
+in4_highest		Highest measured voltage
+in4_reset_history	Write 1 to reset history.
+in4_min_alarm		Undervoltage alarm
+in4_max_alarm		Overvoltage alarm
+in4_enable		Enable/Disable monitoring.
+in4_label		Channel label (VADI3)
+
+in5_input		Output voltage (mV).
+in5_min			Undervoltage threshold
+in5_max			Overvoltage threshold
+in5_lowest		Lowest measured voltage
+in5_highest		Highest measured voltage
+in5_reset_history	Write 1 to reset history.
+in5_min_alarm		Undervoltage alarm
+in5_max_alarm		Overvoltage alarm
+in5_enable		Enable/Disable monitoring.
+in5_label		Channel label (VADI4)
+
+in6_input		Output voltage (mV).
+in6_min			Undervoltage threshold
+in6_max			Overvoltage threshold
+in6_lowest		Lowest measured voltage
+in6_highest		Highest measured voltage
+in6_reset_history	Write 1 to reset history.
+in6_min_alarm		Undervoltage alarm
+in6_max_alarm		Overvoltage alarm
+in6_enable		Enable/Disable monitoring.
+in6_label		Channel label (VADIO1)
+
+in7_input		Output voltage (mV).
+in7_min			Undervoltage threshold
+in7_max			Overvoltage threshold
+in7_lowest		Lowest measured voltage
+in7_highest		Highest measured voltage
+in7_reset_history	Write 1 to reset history.
+in7_min_alarm		Undervoltage alarm
+in7_max_alarm		Overvoltage alarm
+in7_enable		Enable/Disable monitoring.
+in7_label		Channel label (VADIO2)
+
+in8_input		Output voltage (mV).
+in8_min			Undervoltage threshold
+in8_max			Overvoltage threshold
+in8_lowest		Lowest measured voltage
+in8_highest		Highest measured voltage
+in8_reset_history	Write 1 to reset history.
+in8_min_alarm		Undervoltage alarm
+in8_max_alarm		Overvoltage alarm
+in8_enable		Enable/Disable monitoring.
+in8_label		Channel label (VADIO3)
+
+in9_input		Output voltage (mV).
+in9_min			Undervoltage threshold
+in9_max			Overvoltage threshold
+in9_lowest		Lowest measured voltage
+in9_highest		Highest measured voltage
+in9_reset_history	Write 1 to reset history.
+in9_min_alarm		Undervoltage alarm
+in9_max_alarm		Overvoltage alarm
+in9_enable		Enable/Disable monitoring.
+in9_label		Channel label (VADIO4)
+
+in10_input		Output voltage (mV).
+in10_min		Undervoltage threshold
+in10_max		Overvoltage threshold
+in10_lowest		Lowest measured voltage
+in10_highest		Highest measured voltage
+in10_reset_history	Write 1 to reset history.
+in10_min_alarm		Undervoltage alarm
+in10_max_alarm		Overvoltage alarm
+in10_enable		Enable/Disable monitoring.
+in10_label		Channel label (DRNS)
+
+in11_input		Output voltage (mV).
+in11_min		Undervoltage threshold
+in11_max		Overvoltage threshold
+in11_lowest		Lowest measured voltage
+in11_highest		Highest measured voltage
+in11_reset_history	Write 1 to reset history.
+			Also clears fet bad and short fault logs.
+in11_min_alarm		Undervoltage alarm
+in11_max_alarm		Overvoltage alarm
+in11_enable		Enable/Disable monitoring
+in11_fault		Failure in the MOSFET. Either bad or shorted FET.
+in11_label		Channel label (DRAIN)
+
+in12_input		Output voltage (mV).
+in12_min		Undervoltage threshold
+in12_max		Overvoltage threshold
+in12_lowest		Lowest measured voltage
+in12_highest		Highest measured voltage
+in12_reset_history	Write 1 to reset history.
+in12_min_alarm		Undervoltage alarm
+in12_max_alarm		Overvoltage alarm
+in12_enable		Enable/Disable monitoring.
+in12_label		Channel label (ADIN2-ADIN1)
+
+in13_input		Output voltage (mV).
+in13_min		Undervoltage threshold
+in13_max		Overvoltage threshold
+in13_lowest		Lowest measured voltage
+in13_highest		Highest measured voltage
+in13_reset_history	Write 1 to reset history.
+in13_min_alarm		Undervoltage alarm
+in13_max_alarm		Overvoltage alarm
+in13_enable		Enable/Disable monitoring.
+in13_label		Channel label (ADIN4-ADIN3)
+
+in14_input		Output voltage (mV).
+in14_min		Undervoltage threshold
+in14_max		Overvoltage threshold
+in14_lowest		Lowest measured voltage
+in14_highest		Highest measured voltage
+in14_reset_history	Write 1 to reset history.
+in14_min_alarm		Undervoltage alarm
+in14_max_alarm		Overvoltage alarm
+in14_enable		Enable/Disable monitoring.
+in14_label		Channel label (ADIO2-ADIO1)
+
+in15_input		Output voltage (mV).
+in15_min		Undervoltage threshold
+in15_max		Overvoltage threshold
+in15_lowest		Lowest measured voltage
+in15_highest		Highest measured voltage
+in15_reset_history	Write 1 to reset history.
+in15_min_alarm		Undervoltage alarm
+in15_max_alarm		Overvoltage alarm
+in15_enable		Enable/Disable monitoring.
+in15_label		Channel label (ADIO4-ADIO3)
+
+curr1_input		Sense current (mA)
+curr1_min		Undercurrent threshold
+curr1_max		Overcurrent threshold
+curr1_lowest		Lowest measured current
+curr1_highest		Highest measured current
+curr1_reset_history	Write 1 to reset curr1 history.
+			Also clears overcurrent fault logs.
+curr1_min_alarm		Undercurrent alarm
+curr1_max_alarm		Overcurrent alarm
+curr1_crit_alarm        Critical Overcurrent alarm
+curr1_label		Channel label (ISENSE)
+
+power1_input		Power (in uW)
+power1_min		Low power threshold
+power1_max		High power threshold
+power1_input_lowest	Historical minimum power use
+power1_input_highest	Historical maximum power use
+power1_reset_history	Write 1 to reset power1 history.
+			Also clears power fault logs.
+power1_min_alarm	Low power alarm
+power1_max_alarm	High power alarm
+power1_label		Channel label (Power)
+
+energy1_input		Measured energy over time (in microJoule)
+energy1_enable		Enable/Disable Energy accumulation
+
+DebugFs entries
+_______________
+
+The chip also has a fault log register where failures can be logged. Hence,
+as these are logging events, we give access to them in debugfs. Note that
+even if some failure is detected in these logs, it does necessarily mean
+that the failure is still present. As mentioned in the proper Sysfs entries,
+these logs can be cleared by writing in the proper reset_history attribute.
+
+.. warning:: The debugfs interface is subject to change without notice
+             and is only available when the kernel is compiled with
+             ``CONFIG_DEBUG_FS`` defined.
+
+``/sys/kernel/debug/i2c/i2c-[X]/[X]-addr/``
+contains the following attributes:
+
+=======================		==========================================
+power1_failed_fault_log		Set to 1 by a power1 fault occurring.
+power1_good_input_fault_log	Set to 1 by a power1 good input fault occurring at PGIO3.
+in11_fet_short_fault_log	Set to 1 when a FET-short fault occurs.
+in11_fet_bad_fault_log		Set to 1 when a FET-BAD fault occurs.
+in0_lcrit_fault_log		Set to 1 by a VIN undervoltage fault occurring.
+in0_crit_fault_log		Set to 1 by a VIN overvoltage fault occurring.
+curr1_crit_fault_log		Set to 1 by an overcurrent fault occurring.
+======================= 	==========================================
diff --git a/MAINTAINERS b/MAINTAINERS
index b52fc2c777dc..9fa27d0b1890 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14960,6 +14960,7 @@ M:	Nuno Sá <nuno.sa@analog.com>
 L:	linux-hwmon@vger.kernel.org
 S:	Supported
 F:	Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml
+F:	drivers/hwmon/ltc4283.c
 
 LTC4286 HARDWARE MONITOR DRIVER
 M:	Delphine CC Chiu <Delphine_CC_Chiu@Wiwynn.com>
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 157678b821fc..5a5ac9fa4bb1 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1167,6 +1167,18 @@ config SENSORS_LTC4282
 	  This driver can also be built as a module. If so, the module will
 	  be called ltc4282.
 
+config SENSORS_LTC4283
+	tristate "Analog Devices LTC4283"
+	depends on I2C
+	select REGMAP_I2C
+	select AUXILIARY_BUS
+	help
+	  If you say yes here you get support for Analog Devices LTC4283
+	  Negative Voltage Hot Swap Controller I2C interface.
+
+	  This driver can also be built as a module. If so, the module will
+	  be called ltc4283.
+
 config SENSORS_LTQ_CPUTEMP
 	bool "Lantiq cpu temperature sensor driver"
 	depends on SOC_XWAY
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index eade8e3b1bde..f9513b806a43 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -147,6 +147,7 @@ obj-$(CONFIG_SENSORS_LTC4245)	+= ltc4245.o
 obj-$(CONFIG_SENSORS_LTC4260)	+= ltc4260.o
 obj-$(CONFIG_SENSORS_LTC4261)	+= ltc4261.o
 obj-$(CONFIG_SENSORS_LTC4282)	+= ltc4282.o
+obj-$(CONFIG_SENSORS_LTC4283)	+= ltc4283.o
 obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
 obj-$(CONFIG_SENSORS_MACSMC_HWMON)	+= macsmc-hwmon.o
 obj-$(CONFIG_SENSORS_MAX1111)	+= max1111.o
diff --git a/drivers/hwmon/ltc4283.c b/drivers/hwmon/ltc4283.c
new file mode 100644
index 000000000000..402b53f81548
--- /dev/null
+++ b/drivers/hwmon/ltc4283.c
@@ -0,0 +1,1766 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller (HWMON)
+ *
+ * Copyright 2025 Analog Devices Inc.
+ */
+#include <linux/auxiliary_bus.h>
+#include <linux/bitfield.h>
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/bits.h>
+
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/device/devres.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/i2c.h>
+#include <linux/math.h>
+#include <linux/math64.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+
+#include <linux/mod_devicetable.h>
+#include <linux/overflow.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/units.h>
+
+#define LTC4283_SYSTEM_STATUS		0x00
+#define LTC4283_FAULT_STATUS		0x03
+#define   LTC4283_OV_MASK		BIT(0)
+#define   LTC4283_UV_MASK		BIT(1)
+#define   LTC4283_OC_MASK		BIT(2)
+#define   LTC4283_FET_BAD_MASK		BIT(3)
+#define   LTC4283_FET_SHORT_MASK	BIT(6)
+#define LTC4283_FAULT_LOG		0x04
+#define   LTC4283_OV_FAULT_MASK		BIT(0)
+#define   LTC4283_UV_FAULT_MASK		BIT(1)
+#define   LTC4283_OC_FAULT_MASK		BIT(2)
+#define   LTC4283_FET_BAD_FAULT_MASK	BIT(3)
+#define   LTC4283_PGI_FAULT_MASK	BIT(4)
+#define   LTC4283_PWR_FAIL_FAULT_MASK	BIT(5)
+#define   LTC4283_FET_SHORT_FAULT_MASK	BIT(6)
+#define LTC4283_ADC_ALM_LOG_1		0x05
+#define   LTC4283_POWER_LOW_ALM		BIT(0)
+#define   LTC4283_POWER_HIGH_ALM	BIT(1)
+#define   LTC4283_SENSE_LOW_ALM		BIT(4)
+#define   LTC4283_SENSE_HIGH_ALM	BIT(5)
+#define LTC4283_ADC_ALM_LOG_2		0x06
+#define LTC4283_ADC_ALM_LOG_3		0x07
+#define LTC4283_ADC_ALM_LOG_4		0x08
+#define LTC4283_ADC_ALM_LOG_5		0x09
+#define LTC4283_CONTROL_1		0x0a
+#define   LTC4283_PIGIO2_ACLB_MASK	BIT(2)
+#define   LTC4283_PWRGD_RST_CTRL_MASK	BIT(3)
+#define   LTC4283_FET_BAD_OFF_MASK	BIT(4)
+#define   LTC4283_THERM_TMR_MASK	BIT(5)
+#define   LTC4283_DVDT_MASK		BIT(6)
+#define LTC4283_CONTROL_2		0x0b
+#define   LTC4283_OV_RETRY_MASK		BIT(0)
+#define   LTC4283_UV_RETRY_MASK		BIT(1)
+#define   LTC4283_OC_RETRY_MASK		GENMASK(3, 2)
+#define   LTC4283_FET_BAD_RETRY_MASK	GENMASK(5, 4)
+#define   LTC4283_EXT_FAULT_RETRY_MASK	BIT(7)
+#define LTC4283_RESERVED_OC		0x0c
+#define LTC4283_CONFIG_1		0x0d
+#define   LTC4283_FB_MASK		GENMASK(3, 2)
+#define   LTC4283_ILIM_MASK		GENMASK(7, 4)
+#define LTC4283_CONFIG_2		0x0e
+#define   LTC4283_COOLING_DL_MASK	GENMASK(3, 1)
+#define   LTC4283_FTBD_DL_MASK		GENMASK(5, 4)
+#define LTC4283_CONFIG_3		0x0f
+#define   LTC4283_VPWR_DRNS_MASK	BIT(6)
+#define   LTC4283_EXTFLT_TURN_OFF_MASK	BIT(7)
+#define LTC4283_PGIO_CONFIG		0x10
+#define   LTC4283_PGIO1_CFG_MASK	GENMASK(1, 0)
+#define   LTC4283_PGIO2_CFG_MASK	GENMASK(3, 2)
+#define   LTC4283_PGIO3_CFG_MASK	GENMASK(5, 4)
+#define   LTC4283_PGIO4_CFG_MASK	GENMASK(7, 6)
+#define LTC4283_PGIO_CONFIG_2		0x11
+#define   LTC4283_ADC_MASK		GENMASK(2, 0)
+#define LTC4283_ADC_SELECT(c)		(0x13 + (c) / 8)
+#define   LTC4283_ADC_SELECT_MASK(c)	BIT((c) % 8)
+#define LTC4283_SENSE_MIN_TH		0x1b
+#define LTC4283_SENSE_MAX_TH		0x1c
+#define LTC4283_VPWR_MIN_TH		0x1d
+#define LTC4283_VPWR_MAX_TH		0x1e
+#define LTC4283_POWER_MIN_TH		0x1f
+#define LTC4283_POWER_MAX_TH		0x20
+#define LTC4283_ADC_2_MIN_TH(c)		(0x21 + (c) * 2)
+#define LTC4283_ADC_2_MAX_TH(c)		(0x22 + (c) * 2)
+#define LTC4283_ADC_2_MIN_TH_DIFF(c)	(0x39 + (c) * 2)
+#define LTC4283_ADC_2_MAX_TH_DIFF(c)	(0x3a + (c) * 2)
+#define LTC4283_SENSE			0x41
+#define LTC4283_SENSE_MIN		0x42
+#define LTC4283_SENSE_MAX		0x43
+#define LTC4283_VPWR			0x44
+#define LTC4283_VPWR_MIN		0x45
+#define LTC4283_VPWR_MAX		0x46
+#define LTC4283_POWER			0x47
+#define LTC4283_POWER_MIN		0x48
+#define LTC4283_POWER_MAX		0x49
+#define LTC4283_RESERVED_68		0x68
+#define LTC4283_RESERVED_6D		0x6D
+/* get channels from ADC 2 */
+#define LTC4283_ADC_2(c)		(0x4a + (c) * 3)
+#define LTC4283_ADC_2_MIN(c)		(0x4b + (c) * 3)
+#define LTC4283_ADC_2_MAX(c)		(0x4c + (c) * 3)
+#define LTC4283_ADC_2_DIFF(c)		(0x6e + (c) * 3)
+#define LTC4283_ADC_2_MIN_DIFF(c)	(0x6f + (c) * 3)
+#define LTC4283_ADC_2_MAX_DIFF(c)	(0x70 + (c) * 3)
+#define LTC4283_ENERGY			0x7a
+#define LTC4283_METER_CONTROL		0x84
+#define   LTC4283_INTEGRATE_I_MASK	BIT(0)
+#define   LTC4283_METER_HALT_MASK	BIT(6)
+#define LTC4283_RESERVED_86		0x86
+#define LTC4283_RESERVED_8F		0x8F
+#define LTC4283_FAULT_LOG_CTRL		0x90
+#define   LTC4283_FAULT_LOG_EN_MASK	BIT(7)
+#define LTC4283_RESERVED_91		0x91
+#define LTC4283_RESERVED_A1		0xA1
+#define LTC4283_RESERVED_A3		0xA3
+#define LTC4283_RESERVED_AC		0xAC
+#define LTC4283_POWER_PLAY_MSB		0xE7
+#define LTC4283_POWER_PLAY_LSB		0xE8
+#define LTC4283_RESERVED_F1		0xF1
+#define LTC4283_RESERVED_FF		0xFF
+
+/* also applies for differential channels */
+#define LTC4283_ADC1_FS_uV		32768
+#define LTC4283_ADC2_FS_mV		2048
+#define LTC4283_TCONV_uS		64103
+#define LTC4283_VILIM_MIN_uV		15000
+#define LTC4283_VILIM_MAX_uV		30000
+#define LTC4283_VILIM_RANGE	\
+	(LTC4283_VILIM_MAX_uV - LTC4283_VILIM_MIN_uV + 1)
+
+#define LTC4283_PGIO_FUNC_GPIO		2
+#define LTC4283_PGIO2_FUNC_ACLB		3
+
+/* voltage channels */
+enum {
+	LTC4283_CHAN_VIN,
+	LTC4283_CHAN_VPWR,
+	LTC4283_CHAN_ADI_1,
+	LTC4283_CHAN_ADI_2,
+	LTC4283_CHAN_ADI_3,
+	LTC4283_CHAN_ADI_4,
+	LTC4283_CHAN_ADIO_1,
+	LTC4283_CHAN_ADIO_2,
+	LTC4283_CHAN_ADIO_3,
+	LTC4283_CHAN_ADIO_4,
+	LTC4283_CHAN_DRNS,
+	LTC4283_CHAN_DRAIN,
+	/* differential channels */
+	LTC4283_CHAN_ADIN12,
+	LTC4283_CHAN_ADIN34,
+	LTC4283_CHAN_ADIO12,
+	LTC4283_CHAN_ADIO34,
+	LTC4283_CHAN_MAX
+};
+
+/* Just for ease of use on the regmap  */
+#define LTC4283_ADIO34_MAX \
+	LTC4283_ADC_2_MAX_DIFF(LTC4283_CHAN_ADIO34 - LTC4283_CHAN_ADIN12)
+
+struct ltc4283_hwmon {
+	struct regmap *map;
+	/* for the 16bit wide registers */
+	struct regmap *map_word;
+	unsigned long gpio_mask;
+	unsigned long ch_enable_mask;
+	/* in microwatt */
+	long power_max;
+	/* in millivolt */
+	u32 vsense_max;
+	/* in tenths of microohm*/
+	u32 rsense;
+	bool energy_en;
+	bool ext_fault;
+};
+
+static int ltc4283_read_voltage_word(const struct ltc4283_hwmon *st,
+				     u32 reg, u32 fs, long *val)
+{
+	unsigned int __raw;
+	int ret;
+
+	ret = regmap_read(st->map_word, reg, &__raw);
+	if (ret)
+		return ret;
+
+	*val = DIV_ROUND_CLOSEST(__raw * fs, BIT(16));
+	return 0;
+}
+
+static int ltc4283_read_voltage_byte(const struct ltc4283_hwmon *st,
+				     u32 reg, u32 fs, long *val)
+{
+	int ret;
+	u32 in;
+
+	ret = regmap_read(st->map, reg, &in);
+	if (ret)
+		return ret;
+
+	*val = DIV_ROUND_CLOSEST(in * fs, BIT(8));
+	return 0;
+}
+
+static u32 ltc4283_in_reg(u32 attr, u32 channel)
+{
+	switch (attr) {
+	case hwmon_in_input:
+		if (channel == LTC4283_CHAN_VPWR)
+			return LTC4283_VPWR;
+		if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN)
+			return LTC4283_ADC_2(channel - LTC4283_CHAN_ADI_1);
+		return LTC4283_ADC_2_DIFF(channel - LTC4283_CHAN_ADIN12);
+	case hwmon_in_highest:
+		if (channel == LTC4283_CHAN_VPWR)
+			return LTC4283_VPWR_MAX;
+		if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN)
+			return LTC4283_ADC_2_MAX(channel - LTC4283_CHAN_ADI_1);
+		return LTC4283_ADC_2_MAX_DIFF(channel - LTC4283_CHAN_ADIN12);
+	case hwmon_in_lowest:
+		if (channel == LTC4283_CHAN_VPWR)
+			return LTC4283_VPWR_MIN;
+		if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN)
+			return LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1);
+		return LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12);
+	case hwmon_in_max:
+		if (channel == LTC4283_CHAN_VPWR)
+			return LTC4283_VPWR_MAX_TH;
+		if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN)
+			return LTC4283_ADC_2_MAX_TH(channel - LTC4283_CHAN_ADI_1);
+		return LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
+	default:
+		if (channel == LTC4283_CHAN_VPWR)
+			return LTC4283_VPWR_MIN_TH;
+		if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN)
+			return LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1);
+		return LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
+	}
+}
+
+static int ltc4283_read_in_vals(const struct ltc4283_hwmon *st,
+				u32 attr, u32 channel, long *val)
+{
+	u32 reg = ltc4283_in_reg(attr, channel);
+	int ret;
+
+	if (channel < LTC4283_CHAN_ADIN12) {
+		if (attr != hwmon_in_max && attr != hwmon_in_min)
+			return ltc4283_read_voltage_word(st, reg,
+							 LTC4283_ADC2_FS_mV,
+							 val);
+
+		return ltc4283_read_voltage_byte(st, reg,
+						 LTC4283_ADC2_FS_mV, val);
+	}
+
+	if (attr != hwmon_in_max && attr != hwmon_in_min)
+		ret = ltc4283_read_voltage_word(st, reg,
+						LTC4283_ADC1_FS_uV, val);
+	else
+		ret = ltc4283_read_voltage_byte(st, reg,
+						LTC4283_ADC1_FS_uV, val);
+	if (ret)
+		return ret;
+
+	*val = DIV_ROUND_CLOSEST(*val, MILLI);
+	return 0;
+}
+
+static int ltc4283_read_alarm(struct ltc4283_hwmon *st, u32 reg,
+			      u32 mask, long *val)
+{
+	u32 alarm;
+	int ret;
+
+	ret = regmap_read(st->map, reg, &alarm);
+	if (ret)
+		return ret;
+
+	*val = !!(alarm & mask);
+
+	/* If not status/fault logs, clear the alarm after reading it. */
+	if (reg != LTC4283_FAULT_STATUS && reg != LTC4283_FAULT_LOG)
+		return regmap_clear_bits(st->map, reg, mask);
+
+	return 0;
+}
+
+static int ltc4283_read_in_alarm(struct ltc4283_hwmon *st, u32 channel,
+				 bool max_alm, long *val)
+{
+	if (channel == LTC4283_VPWR)
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
+					  BIT(2 + max_alm), val);
+
+	if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_ADI_4) {
+		u32 bit = (channel - LTC4283_CHAN_ADI_1) * 2;
+		/*
+		 * Lower channels go to higher bits. We also want to go +1 down
+		 * in the min_alarm case.
+		 */
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_2,
+					  BIT(7 - bit - !max_alm), val);
+	}
+
+	if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) {
+		u32 bit = (channel - LTC4283_CHAN_ADIO_1) * 2;
+
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_3,
+					  BIT(7 - bit - !max_alm), val);
+	}
+
+	if (channel >= LTC4283_CHAN_ADIN12 && channel <= LTC4283_CHAN_ADIN34) {
+		u32 bit = (channel - LTC4283_CHAN_ADIN12) * 2;
+
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_5,
+					  BIT(7 - bit - !max_alm), val);
+	}
+
+	if (channel == LTC4283_CHAN_DRNS)
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4,
+					  BIT(6 + max_alm), val);
+
+	return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4, BIT(4 + max_alm),
+				  val);
+}
+
+static int ltc4283_read_in(struct ltc4283_hwmon *st, u32 attr, u32 channel,
+			   long *val)
+{
+	switch (attr) {
+	case hwmon_in_input:
+		if (!test_bit(channel, &st->ch_enable_mask))
+			return -ENODATA;
+
+		return ltc4283_read_in_vals(st, attr, channel, val);
+	case hwmon_in_highest:
+	case hwmon_in_lowest:
+	case hwmon_in_max:
+	case hwmon_in_min:
+		return ltc4283_read_in_vals(st, attr, channel, val);
+	case hwmon_in_max_alarm:
+		return ltc4283_read_in_alarm(st, channel, true, val);
+	case hwmon_in_min_alarm:
+		return ltc4283_read_in_alarm(st, channel, false, val);
+	case hwmon_in_crit_alarm:
+		return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
+					  LTC4283_OV_MASK, val);
+	case hwmon_in_lcrit_alarm:
+		return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
+					  LTC4283_UV_MASK, val);
+	case hwmon_in_fault:
+		/*
+		 * We report failure if we detect either a fer_bad or a
+		 * fet_short in the status register.
+		 */
+		return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
+					  LTC4283_FET_BAD_MASK | LTC4283_FET_SHORT_MASK, val);
+	case hwmon_in_enable:
+		*val = test_bit(channel, &st->ch_enable_mask);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+	return 0;
+}
+
+static int ltc4283_read_current_word(const struct ltc4283_hwmon *st, u32 reg,
+				     long *val)
+{
+	u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI;
+	unsigned int __raw;
+	int ret;
+
+	ret = regmap_read(st->map_word, reg, &__raw);
+	if (ret)
+		return ret;
+
+	*val = DIV64_U64_ROUND_CLOSEST(__raw * temp,
+				       BIT_ULL(16) * st->rsense);
+
+	return 0;
+}
+
+static int ltc4283_read_current_byte(const struct ltc4283_hwmon *st, u32 reg,
+				     long *val)
+{
+	u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI;
+	u32 curr;
+	int ret;
+
+	ret = regmap_read(st->map, reg, &curr);
+	if (ret)
+		return ret;
+
+	*val = DIV_ROUND_CLOSEST_ULL(curr * temp, BIT(8) * st->rsense);
+	return 0;
+}
+
+static int ltc4283_read_curr(struct ltc4283_hwmon *st, u32 attr, long *val)
+{
+	switch (attr) {
+	case hwmon_curr_input:
+		return ltc4283_read_current_word(st, LTC4283_SENSE, val);
+	case hwmon_curr_highest:
+		return ltc4283_read_current_word(st, LTC4283_SENSE_MAX, val);
+	case hwmon_curr_lowest:
+		return ltc4283_read_current_word(st, LTC4283_SENSE_MIN, val);
+	case hwmon_curr_max:
+		return ltc4283_read_current_byte(st, LTC4283_SENSE_MAX_TH, val);
+	case hwmon_curr_min:
+		return ltc4283_read_current_byte(st, LTC4283_SENSE_MIN_TH, val);
+	case hwmon_curr_max_alarm:
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
+					  LTC4283_SENSE_HIGH_ALM, val);
+	case hwmon_curr_min_alarm:
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
+					  LTC4283_SENSE_LOW_ALM, val);
+	case hwmon_curr_crit_alarm:
+		return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS,
+					  LTC4283_OC_MASK, val);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ltc4283_read_power_word(const struct ltc4283_hwmon *st,
+				   u32 reg, long *val)
+{
+	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
+	unsigned int __raw;
+	int ret;
+
+	ret = regmap_read(st->map_word, reg, &__raw);
+	if (ret)
+		return ret;
+
+	/*
+	 * Power is given by:
+	 *     P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense)
+	 */
+	*val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense);
+
+	return 0;
+}
+
+static int ltc4283_read_power_byte(const struct ltc4283_hwmon *st,
+				   u32 reg, long *val)
+{
+	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
+	u32 power;
+	int ret;
+
+	ret = regmap_read(st->map, reg, &power);
+	if (ret)
+		return ret;
+
+	*val = DIV_ROUND_CLOSEST_ULL(power * temp, BIT(8) * st->rsense);
+
+	return 0;
+}
+
+static int ltc4283_read_power(struct ltc4283_hwmon *st, u32 attr, long *val)
+{
+	switch (attr) {
+	case hwmon_power_input:
+		return ltc4283_read_power_word(st, LTC4283_POWER, val);
+	case hwmon_power_input_highest:
+		return ltc4283_read_power_word(st, LTC4283_POWER_MAX, val);
+	case hwmon_power_input_lowest:
+		return ltc4283_read_power_word(st, LTC4283_POWER_MIN, val);
+	case hwmon_power_max_alarm:
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
+					  LTC4283_POWER_HIGH_ALM, val);
+	case hwmon_power_min_alarm:
+		return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1,
+					  LTC4283_POWER_LOW_ALM, val);
+	case hwmon_power_max:
+		return ltc4283_read_power_byte(st, LTC4283_POWER_MAX_TH, val);
+	case hwmon_power_min:
+		return ltc4283_read_power_byte(st, LTC4283_POWER_MIN_TH, val);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ltc4283_read_energy(struct ltc4283_hwmon *st, u32 attr, s64 *val)
+{
+	u64 temp = LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV, energy, temp_2;
+	__be64 raw;
+	int ret;
+
+	if (!st->energy_en)
+		return -ENODATA;
+
+	ret = regmap_bulk_read(st->map, LTC4283_ENERGY, &raw, sizeof(raw));
+	if (ret)
+		return ret;
+
+	energy =  be64_to_cpu(raw) >> 16;
+
+	/*
+	 * The formula for energy is given by:
+	 *	E = CODE(48b) * 32.768mV * 2.048V * Tconv / 2^24 * Rsense
+	 *
+	 * As Rsense can have tenths of micro-ohm resolution, we need to
+	 * multiply by DECA to get microjoule.
+	 */
+	if (check_mul_overflow(temp * LTC4283_TCONV_uS, energy, &temp_2)) {
+		/*
+		 * We multiply again by 1000 to make sure that we don't get 0
+		 * in the following division which could happen for big rsense
+		 * values. OTOH, we then divide energy first by 1000 so that
+		 * we do not overflow u64 again for very small rsense values.
+		 * We add 100 factor for proper conversion to microjoule.
+		 */
+		temp_2 = DIV64_U64_ROUND_CLOSEST(temp * LTC4283_TCONV_uS * MILLI,
+						 BIT_ULL(24) * st->rsense);
+		energy = DIV_ROUND_CLOSEST_ULL(energy, MILLI * CENTI) * temp_2;
+	} else {
+		/* Put rsense back into nanoohm so we get microjoule. */
+		energy = DIV64_U64_ROUND_CLOSEST(temp_2, BIT_ULL(24) * st->rsense * CENTI);
+	}
+
+	*val = energy;
+	return 0;
+}
+
+static int ltc4283_read(struct device *dev, enum hwmon_sensor_types type,
+			u32 attr, int channel, long *val)
+{
+	struct ltc4283_hwmon *st = dev_get_drvdata(dev);
+
+	switch (type) {
+	case hwmon_in:
+		return ltc4283_read_in(st, attr, channel, val);
+	case hwmon_curr:
+		return ltc4283_read_curr(st, attr, val);
+	case hwmon_power:
+		return ltc4283_read_power(st, attr, val);
+	case hwmon_energy:
+		*val = st->energy_en;
+		return 0;
+	case hwmon_energy64:
+		return ltc4283_read_energy(st, attr, (s64 *)val);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ltc4283_write_power_byte(const struct ltc4283_hwmon *st, u32 reg,
+				    long val)
+{
+	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
+	u32 __raw;
+
+	if (val > st->power_max)
+		val = st->power_max;
+
+	__raw = DIV64_U64_ROUND_CLOSEST(val * BIT_ULL(8) * st->rsense, temp);
+
+	return regmap_write(st->map, reg, __raw);
+}
+
+static int ltc4283_write_power_word(const struct ltc4283_hwmon *st,
+				    u32 reg, long val)
+{
+	u64 temp = st->rsense * BIT_ULL(16), temp_2;
+	u16 __raw;
+
+	if (check_mul_overflow(val, temp, &temp_2)) {
+		temp = DIV_ROUND_CLOSEST_ULL(temp, DECA * MILLI);
+		__raw = DIV_ROUND_CLOSEST_ULL(temp * val, LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV);
+	} else {
+		temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
+		__raw = DIV64_U64_ROUND_CLOSEST(temp_2, temp);
+	}
+
+	return regmap_write(st->map_word, reg, __raw);
+}
+
+static int ltc4283_reset_power_hist(struct ltc4283_hwmon *st)
+{
+	int ret;
+
+	ret = ltc4283_write_power_word(st, LTC4283_POWER_MIN, st->power_max);
+	if (ret)
+		return ret;
+
+	ret = ltc4283_write_power_word(st, LTC4283_POWER_MAX, 0);
+	if (ret)
+		return ret;
+
+	/* Clear possible power faults. */
+	return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
+				 LTC4283_PWR_FAIL_FAULT_MASK | LTC4283_PGI_FAULT_MASK);
+}
+
+static int ltc4283_write_power(struct ltc4283_hwmon *st, u32 attr, long val)
+{
+	switch (attr) {
+	case hwmon_power_max:
+		return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, val);
+	case hwmon_power_min:
+		return ltc4283_write_power_byte(st, LTC4283_POWER_MIN_TH, val);
+	case hwmon_power_reset_history:
+		return ltc4283_reset_power_hist(st);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ltc4283_write_in_history(struct ltc4283_hwmon *st, u32 reg,
+				    long lowest, u32 fs)
+{
+	u32 __raw;
+	int ret;
+
+	__raw = DIV_ROUND_CLOSEST(BIT(16) * lowest, fs);
+	if (__raw == BIT(16))
+		__raw = U16_MAX;
+
+	ret = regmap_write(st->map_word, reg, __raw);
+	if (ret)
+		return ret;
+
+	return regmap_write(st->map_word, reg + 1, 0);
+}
+
+static int ltc4283_write_in_byte(const struct ltc4283_hwmon *st,
+				 u32 reg, u32 fs, long val)
+{
+	u32 __raw;
+
+	val = clamp_val(val, 0, fs);
+	__raw = DIV_ROUND_CLOSEST(val * BIT(8), fs);
+
+	return regmap_write(st->map, reg, __raw);
+}
+
+static int ltc4283_reset_in_hist(struct ltc4283_hwmon *st, u32 channel)
+{
+	u32 reg, fs;
+	int ret;
+
+	/*
+	 * Make sure to clear possible under/over voltage faults. Otherwise the
+	 * chip won't latch on again.
+	 */
+	if (channel == LTC4283_CHAN_VIN)
+		return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
+					 LTC4283_OV_FAULT_MASK | LTC4283_UV_FAULT_MASK);
+
+	if (channel == LTC4283_CHAN_VPWR)
+		return ltc4283_write_in_history(st, LTC4283_VPWR_MIN,
+						LTC4283_ADC2_FS_mV,
+						LTC4283_ADC2_FS_mV);
+
+	if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) {
+		fs = LTC4283_ADC2_FS_mV;
+		reg = LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1);
+	} else {
+		fs = LTC4283_ADC1_FS_uV;
+		reg = LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12);
+	}
+
+	ret = ltc4283_write_in_history(st, reg, fs, fs);
+	if (ret)
+		return ret;
+	if (channel != LTC4283_CHAN_DRAIN)
+		return 0;
+
+	/* Then, let's also clear possible fet faults. Same as above. */
+	return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
+				 LTC4283_FET_BAD_FAULT_MASK | LTC4283_FET_SHORT_FAULT_MASK);
+}
+
+static int ltc4283_write_in_en(struct ltc4283_hwmon *st, u32 channel, bool en)
+{
+	unsigned int bit, adc_idx = channel - LTC4283_CHAN_ADI_1;
+	unsigned int reg = LTC4283_ADC_SELECT(adc_idx);
+	int ret;
+
+	bit = LTC4283_ADC_SELECT_MASK(adc_idx);
+	if (channel > LTC4283_CHAN_DRAIN)
+		/* Account for two reserved fields after DRAIN. */
+		bit <<= 2;
+
+	if (en)
+		ret = regmap_set_bits(st->map, reg, bit);
+	else
+		ret = regmap_clear_bits(st->map, reg, bit);
+	if (ret)
+		return ret;
+
+	__assign_bit(channel, &st->ch_enable_mask, en);
+	return 0;
+}
+
+static int ltc4283_write_minmax(struct ltc4283_hwmon *st, long val,
+				u32 channel, bool is_max)
+{
+	u32 reg;
+
+	if (channel == LTC4283_CHAN_VPWR) {
+		if (is_max)
+			return ltc4283_write_in_byte(st, LTC4283_VPWR_MAX_TH,
+						     LTC4283_ADC2_FS_mV, val);
+
+		return ltc4283_write_in_byte(st, LTC4283_VPWR_MIN_TH,
+					     LTC4283_ADC2_FS_mV, val);
+	}
+
+	if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) {
+		if (is_max) {
+			reg = LTC4283_ADC_2_MAX_TH(channel - LTC4283_CHAN_ADI_1);
+			return ltc4283_write_in_byte(st, reg,
+						     LTC4283_ADC2_FS_mV, val);
+		}
+
+		reg = LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1);
+		return ltc4283_write_in_byte(st, reg, LTC4283_ADC2_FS_mV, val);
+	}
+
+	if (is_max) {
+		reg = LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
+		return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV,
+					     val * MILLI);
+	}
+
+	reg = LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12);
+	return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, val * MILLI);
+}
+
+static int ltc4283_write_in(struct ltc4283_hwmon *st, u32 attr, long val,
+			    int channel)
+{
+	switch (attr) {
+	case hwmon_in_max:
+		return ltc4283_write_minmax(st, val, channel, true);
+	case hwmon_in_min:
+		return ltc4283_write_minmax(st, val, channel, false);
+	case hwmon_in_reset_history:
+		return ltc4283_reset_in_hist(st, channel);
+	case hwmon_in_enable:
+		return ltc4283_write_in_en(st, channel, !!val);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ltc4283_write_curr_byte(const struct ltc4283_hwmon *st,
+				   u32 reg, long val)
+{
+	u32 temp = LTC4283_ADC1_FS_uV * DECA * MILLI;
+	u32 reg_val;
+
+	reg_val = DIV_ROUND_CLOSEST_ULL(val * BIT_ULL(8) * st->rsense, temp);
+	return regmap_write(st->map, reg, reg_val);
+}
+
+static int ltc4283_write_curr_history(struct ltc4283_hwmon *st)
+{
+	int ret;
+
+	ret = ltc4283_write_in_history(st, LTC4283_SENSE_MIN, st->vsense_max,
+				       LTC4283_ADC1_FS_uV);
+	if (ret)
+		return ret;
+
+	/* Now, let's also clear possible overcurrent logs. */
+	return regmap_clear_bits(st->map, LTC4283_FAULT_LOG,
+				 LTC4283_OC_FAULT_MASK);
+}
+
+static int ltc4283_write_curr(struct ltc4283_hwmon *st, u32 attr, long val)
+{
+	switch (attr) {
+	case hwmon_curr_max:
+		return ltc4283_write_curr_byte(st, LTC4283_SENSE_MAX_TH, val);
+	case hwmon_curr_min:
+		return ltc4283_write_curr_byte(st, LTC4283_SENSE_MIN_TH, val);
+	case hwmon_curr_reset_history:
+		return ltc4283_write_curr_history(st);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ltc4283_energy_enable_set(struct ltc4283_hwmon *st, long val)
+{
+	int ret;
+
+	/* Setting the bit halts the meter. */
+	val = !!val;
+	ret = regmap_update_bits(st->map, LTC4283_METER_CONTROL,
+				 LTC4283_METER_HALT_MASK,
+				 FIELD_PREP(LTC4283_METER_HALT_MASK, !val));
+	if (ret)
+		return ret;
+
+	st->energy_en = val;
+
+	return 0;
+}
+
+static int ltc4283_write(struct device *dev, enum hwmon_sensor_types type,
+			 u32 attr, int channel, long val)
+{
+	struct ltc4283_hwmon *st = dev_get_drvdata(dev);
+
+	switch (type) {
+	case hwmon_power:
+		return ltc4283_write_power(st, attr, val);
+	case hwmon_in:
+		return ltc4283_write_in(st, attr, val, channel);
+	case hwmon_curr:
+		return ltc4283_write_curr(st, attr, val);
+	case hwmon_energy:
+		return ltc4283_energy_enable_set(st, val);
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static umode_t ltc4283_in_is_visible(const struct ltc4283_hwmon *st,
+				     u32 attr, int channel)
+{
+	/* If ADIO is set as a GPIO, don´t make it visible. */
+	if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) {
+		/* ADIOX pins come at index 0 in the gpio mask. */
+		channel -= LTC4283_CHAN_ADIO_1;
+		if (test_bit(channel, &st->gpio_mask))
+			return 0;
+	}
+
+	/* Also take care of differential channels. */
+	if (channel >= LTC4283_CHAN_ADIO12 && channel <= LTC4283_CHAN_ADIO34) {
+		channel -= LTC4283_CHAN_ADIO12;
+		/* If one channel in the pair is used, make it invisible. */
+		if (test_bit(channel * 2, &st->gpio_mask) ||
+		    test_bit(channel * 2 + 1, &st->gpio_mask))
+			return 0;
+	}
+
+	switch (attr) {
+	case hwmon_in_input:
+	case hwmon_in_highest:
+	case hwmon_in_lowest:
+	case hwmon_in_max_alarm:
+	case hwmon_in_min_alarm:
+	case hwmon_in_label:
+	case hwmon_in_lcrit_alarm:
+	case hwmon_in_crit_alarm:
+	case hwmon_in_fault:
+		return 0444;
+	case hwmon_in_max:
+	case hwmon_in_min:
+	case hwmon_in_enable:
+		return 0644;
+	case hwmon_in_reset_history:
+		return 0200;
+	default:
+		return 0;
+	}
+}
+
+static umode_t ltc4283_curr_is_visible(u32 attr)
+{
+	switch (attr) {
+	case hwmon_curr_input:
+	case hwmon_curr_highest:
+	case hwmon_curr_lowest:
+	case hwmon_curr_max_alarm:
+	case hwmon_curr_min_alarm:
+	case hwmon_curr_crit_alarm:
+	case hwmon_curr_label:
+		return 0444;
+	case hwmon_curr_max:
+	case hwmon_curr_min:
+		return 0644;
+	case hwmon_curr_reset_history:
+		return 0200;
+	default:
+		return 0;
+	}
+}
+
+static umode_t ltc4283_power_is_visible(u32 attr)
+{
+	switch (attr) {
+	case hwmon_power_input:
+	case hwmon_power_input_highest:
+	case hwmon_power_input_lowest:
+	case hwmon_power_label:
+	case hwmon_power_max_alarm:
+	case hwmon_power_min_alarm:
+		return 0444;
+	case hwmon_power_max:
+	case hwmon_power_min:
+		return 0644;
+	case hwmon_power_reset_history:
+		return 0200;
+	default:
+		return 0;
+	}
+}
+
+static umode_t ltc4283_is_visible(const void *data,
+				  enum hwmon_sensor_types type,
+				  u32 attr, int channel)
+{
+	switch (type) {
+	case hwmon_in:
+		return ltc4283_in_is_visible(data, attr, channel);
+	case hwmon_curr:
+		return ltc4283_curr_is_visible(attr);
+	case hwmon_power:
+		return ltc4283_power_is_visible(attr);
+	case hwmon_energy:
+		/* hwmon_energy_enable */
+		return 0644;
+	case hwmon_energy64:
+		/* hwmon_energy_input */
+		return 0444;
+	default:
+		return 0;
+	}
+}
+
+static const char * const ltc4283_in_strs[] = {
+	"VIN", "VPWR", "VADI1", "VADI2", "VADI3", "VADI4", "VADIO1", "VADIO2",
+	"VADIO3", "VADIO4", "DRNS", "DRAIN", "ADIN2-ADIN1", "ADIN4-ADIN3",
+	"ADIO2-ADIO1", "ADIO4-ADIO3"
+};
+
+static int ltc4283_read_labels(struct device *dev,
+			       enum hwmon_sensor_types type,
+			       u32 attr, int channel, const char **str)
+{
+	switch (type) {
+	case hwmon_in:
+		*str = ltc4283_in_strs[channel];
+		return 0;
+	case hwmon_curr:
+		*str = "ISENSE";
+		return 0;
+	case hwmon_power:
+		*str = "Power";
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+/*
+ * Set max limits for ISENSE and Power as that depends on the max voltage on
+ * rsense that is defined in ILIM_ADJUST. This is specially important for power
+ * because for some rsense and vfsout values, if we allow the default raw 255
+ * value, that would overflow long in 32bit archs when reading back the max
+ * power limit.
+ */
+static int ltc4283_set_max_limits(struct ltc4283_hwmon *st, struct device *dev)
+{
+	u32 temp = st->vsense_max * DECA * MICRO;
+	int ret;
+
+	ret = ltc4283_write_in_byte(st, LTC4283_SENSE_MAX_TH, LTC4283_ADC1_FS_uV,
+				    st->vsense_max * MILLI);
+	if (ret)
+		return ret;
+
+	/* Power is given by ISENSE * Vout. */
+	st->power_max = DIV_ROUND_CLOSEST(temp, st->rsense) * LTC4283_ADC2_FS_mV;
+	return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, st->power_max);
+}
+
+static int ltc4283_parse_array_prop(const struct ltc4283_hwmon *st,
+				    struct device *dev, const char *prop,
+				    const u32 *vals, u32 n_vals)
+{
+	u32 prop_val;
+	int ret;
+	u32 i;
+
+	ret = device_property_read_u32(dev, prop, &prop_val);
+	if (ret)
+		return n_vals;
+
+	for (i = 0; i < n_vals; i++) {
+		if (prop_val != vals[i])
+			continue;
+
+		return i;
+	}
+
+	return dev_err_probe(dev, -EINVAL,
+			     "Invalid %s property value %u, expected one of: %*ph\n",
+			     prop, prop_val, n_vals, vals);
+}
+
+static int ltc4283_get_defaults(struct ltc4283_hwmon *st)
+{
+	u32 reg_val, ilm_adjust, c;
+	int ret;
+
+	ret = regmap_read(st->map, LTC4283_METER_CONTROL, &reg_val);
+	if (ret)
+		return ret;
+
+	st->energy_en = !FIELD_GET(LTC4283_METER_HALT_MASK, reg_val);
+
+	ret = regmap_read(st->map, LTC4283_CONFIG_1, &reg_val);
+	if (ret)
+		return ret;
+
+	ilm_adjust = FIELD_GET(LTC4283_ILIM_MASK, reg_val);
+	st->vsense_max = LTC4283_VILIM_MIN_uV / MILLI + ilm_adjust;
+
+	/* VPWR and VIN are always enabled */
+	__set_bit(LTC4283_CHAN_VIN, &st->ch_enable_mask);
+	__set_bit(LTC4283_CHAN_VPWR, &st->ch_enable_mask);
+	for (c = LTC4283_CHAN_ADI_1; c < LTC4283_CHAN_MAX; c++) {
+		u32 chan = c - LTC4283_CHAN_ADI_1, bit;
+
+		ret = regmap_read(st->map, LTC4283_ADC_SELECT(chan), &reg_val);
+		if (ret)
+			return ret;
+
+		bit = LTC4283_ADC_SELECT_MASK(chan);
+		if (c > LTC4283_CHAN_DRAIN)
+			/* account for two reserved fields after DRAIN */
+			bit <<= 2;
+
+		if (!(bit & reg_val))
+			continue;
+
+		__set_bit(c, &st->ch_enable_mask);
+	}
+
+	return 0;
+}
+
+static const char * const ltc4283_pgio1_funcs[] = {
+	"inverted_power_good", "power_good", "gpio"
+};
+
+static const char * const ltc4283_pgio2_funcs[] = {
+	 "inverted_power_good", "power_good", "gpio", "active_current_limiting"
+};
+
+static const char * const ltc4283_pgio3_funcs[] = {
+	"inverted_power_good_input", "power_good_input", "gpio"
+};
+
+static const char * const ltc4283_pgio4_funcs[] = {
+	"inverted_external_fault", "external_fault", "gpio"
+};
+
+enum {
+	LTC4283_PIN_ADIO1,
+	LTC4283_PIN_ADIO2,
+	LTC4283_PIN_ADIO3,
+	LTC4283_PIN_ADIO4,
+	LTC4283_PIN_PGIO1,
+	LTC4283_PIN_PGIO2,
+	LTC4283_PIN_PGIO3,
+	LTC4283_PIN_PGIO4,
+};
+
+static int ltc4283_pgio_config(struct ltc4283_hwmon *st, struct device *dev)
+{
+	int ret, func;
+
+	func = device_property_match_property_string(dev, "adi,pgio1-func",
+						     ltc4283_pgio1_funcs,
+						     ARRAY_SIZE(ltc4283_pgio1_funcs));
+	if (func < 0 && func != -EINVAL)
+		return dev_err_probe(dev, func,
+				     "Invalid adi,pgio1-func property\n");
+	if (func >= 0) {
+		if (func == LTC4283_PGIO_FUNC_GPIO) {
+			__set_bit(LTC4283_PIN_PGIO1, &st->gpio_mask);
+			/* If GPIO, default to an input pin. */
+			func++;
+		}
+
+		ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
+					 LTC4283_PGIO1_CFG_MASK,
+					 FIELD_PREP(LTC4283_PGIO1_CFG_MASK, func));
+		if (ret)
+			return ret;
+	}
+
+	func = device_property_match_property_string(dev, "adi,pgio2-func",
+						     ltc4283_pgio2_funcs,
+						     ARRAY_SIZE(ltc4283_pgio2_funcs));
+
+	if (func < 0 && func != -EINVAL)
+		return dev_err_probe(dev, func,
+				     "Invalid adi,pgio2-func property\n");
+	if (func >= 0) {
+		if (func != LTC4283_PGIO2_FUNC_ACLB) {
+			if (func == LTC4283_PGIO_FUNC_GPIO)  {
+				__set_bit(LTC4283_PIN_PGIO2, &st->gpio_mask);
+				func++;
+			}
+
+			ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
+						 LTC4283_PGIO2_CFG_MASK,
+						 FIELD_PREP(LTC4283_PGIO2_CFG_MASK, func));
+		} else {
+			ret = regmap_set_bits(st->map, LTC4283_CONTROL_1,
+					      LTC4283_PIGIO2_ACLB_MASK);
+		}
+
+		if (ret)
+			return ret;
+	}
+
+	func = device_property_match_property_string(dev, "adi,pgio3-func",
+						     ltc4283_pgio3_funcs,
+						     ARRAY_SIZE(ltc4283_pgio3_funcs));
+
+	if (func < 0 && func != -EINVAL)
+		return dev_err_probe(dev, func,
+				     "Invalid adi,pgio3-func property\n");
+	if (func >= 0) {
+		if (func == LTC4283_PGIO_FUNC_GPIO) {
+			__set_bit(LTC4283_PIN_PGIO3, &st->gpio_mask);
+			func++;
+		}
+
+		ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
+					 LTC4283_PGIO3_CFG_MASK,
+					 FIELD_PREP(LTC4283_PGIO3_CFG_MASK, func));
+		if (ret)
+			return ret;
+	}
+
+	func = device_property_match_property_string(dev, "adi,pgio4-func",
+						     ltc4283_pgio4_funcs,
+						     ARRAY_SIZE(ltc4283_pgio4_funcs));
+
+	if (func < 0 && func != -EINVAL)
+		return dev_err_probe(dev, func,
+				     "Invalid adi,pgio4-func property\n");
+	if (func >= 0) {
+		if (func == LTC4283_PGIO_FUNC_GPIO) {
+			__set_bit(LTC4283_PIN_PGIO4, &st->gpio_mask);
+			func++;
+		} else {
+			st->ext_fault = true;
+		}
+
+		ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG,
+					 LTC4283_PGIO4_CFG_MASK,
+					 FIELD_PREP(LTC4283_PGIO4_CFG_MASK, func));
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ltc4283_adio_config(struct ltc4283_hwmon *st, struct device *dev,
+			       const char *prop, u32 pin)
+{
+	u32 adc_idx;
+	int ret;
+
+	if (!device_property_read_bool(dev, prop))
+		return 0;
+
+	adc_idx = LTC4283_CHAN_ADIO_1 - LTC4283_CHAN_ADI_1 + pin;
+	ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(adc_idx),
+				LTC4283_ADC_SELECT_MASK(adc_idx));
+	if (ret)
+		return ret;
+
+	__set_bit(pin, &st->gpio_mask);
+	return 0;
+}
+
+static int ltc4283_pin_config(struct ltc4283_hwmon *st, struct device *dev)
+{
+	int ret;
+
+	ret = ltc4283_pgio_config(st, dev);
+	if (ret)
+		return ret;
+
+	ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio1", LTC4283_PIN_ADIO1);
+	if (ret)
+		return ret;
+
+	ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio2", LTC4283_PIN_ADIO2);
+	if (ret)
+		return ret;
+
+	ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio3", LTC4283_PIN_ADIO3);
+	if (ret)
+		return ret;
+
+	return ltc4283_adio_config(st, dev, "adi,gpio-on-adio4", LTC4283_PIN_ADIO4);
+}
+
+static const char * const ltc4283_oc_fet_retry[] = {
+	"latch-off", "1", "7", "unlimited"
+};
+
+static const u32 ltc4283_fb_factor[] = {
+	100, 50, 20, 10
+};
+
+static const u32 ltc4283_cooling_dl[] = {
+	512, 1002, 2005, 4100, 8190, 16400, 32800, 65600
+};
+
+static const u32 ltc4283_fet_bad_delay[] = {
+	256, 512, 1002, 2005
+};
+
+static int ltc4283_setup(struct ltc4283_hwmon *st, struct device *dev)
+{
+	u32 val, chan;
+	int ret;
+
+	/* The part has an eeprom so let's get the needed defaults from it */
+	ret = ltc4283_get_defaults(st);
+	if (ret)
+		return ret;
+
+	/* default to 1 micro ohm so we can probe without FW properties */
+	st->rsense = 1 * MICRO;
+	ret = device_property_read_u32(dev, "adi,rsense-nano-ohms",
+				       &st->rsense);
+	if (!ret) {
+		if (st->rsense < CENTI)
+			return dev_err_probe(dev, -EINVAL,
+					     "adi,rsense-nano-ohms too small (< %lu)\n",
+					     CENTI);
+	}
+
+	/*
+	 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which
+	 * means we need nano in the bindings. However, to make things easier to
+	 * handle (with respect to overflows) we divide it by 100 as we don't
+	 * really need the last two digits.
+	 */
+	st->rsense /= CENTI;
+
+	ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt",
+				       &st->vsense_max);
+	if (!ret) {
+		u32 reg_val;
+
+		if (!in_range(st->vsense_max, LTC4283_VILIM_MIN_uV,
+			      LTC4283_VILIM_RANGE)) {
+			return dev_err_probe(dev, -EINVAL,
+					     "adi,current-limit-sense-microvolt (%u) out of range [%u %u]\n",
+					     st->vsense_max, LTC4283_VILIM_MIN_uV,
+					     LTC4283_VILIM_MAX_uV);
+		}
+
+		st->vsense_max /= MILLI;
+		reg_val = FIELD_PREP(LTC4283_ILIM_MASK,
+				     st->vsense_max - LTC4283_VILIM_MIN_uV / MILLI);
+		ret = regmap_update_bits(st->map, LTC4283_CONFIG_1,
+					 LTC4283_ILIM_MASK, reg_val);
+		if (ret)
+			return ret;
+	}
+
+	ret = ltc4283_parse_array_prop(st, dev, "adi,current-limit-foldback-factor",
+				       ltc4283_fb_factor, ARRAY_SIZE(ltc4283_fb_factor));
+	if (ret < 0)
+		return ret;
+	if (ret < ARRAY_SIZE(ltc4283_fb_factor)) {
+		ret = regmap_update_bits(st->map, LTC4283_CONFIG_1, LTC4283_FB_MASK,
+					 FIELD_PREP(LTC4283_FB_MASK, ret));
+		if (ret)
+			return ret;
+	}
+
+	ret = ltc4283_parse_array_prop(st, dev, "adi,cooling-delay-ms",
+				       ltc4283_cooling_dl, ARRAY_SIZE(ltc4283_cooling_dl));
+	if (ret < 0)
+		return ret;
+	if (ret < ARRAY_SIZE(ltc4283_cooling_dl)) {
+		ret = regmap_update_bits(st->map, LTC4283_CONFIG_2, LTC4283_COOLING_DL_MASK,
+					 FIELD_PREP(LTC4283_COOLING_DL_MASK, ret));
+		if (ret)
+			return ret;
+	}
+
+	ret = ltc4283_parse_array_prop(st, dev, "adi,fet-bad-timer-delay-ms",
+				       ltc4283_fet_bad_delay, ARRAY_SIZE(ltc4283_fet_bad_delay));
+	if (ret < 0)
+		return ret;
+	if (ret < ARRAY_SIZE(ltc4283_fet_bad_delay)) {
+		ret = regmap_update_bits(st->map, LTC4283_CONFIG_2, LTC4283_FTBD_DL_MASK,
+					 FIELD_PREP(LTC4283_FTBD_DL_MASK, ret));
+		if (ret)
+			return ret;
+	}
+
+	ret = ltc4283_set_max_limits(st, dev);
+	if (ret)
+		return ret;
+
+	ret = ltc4283_pin_config(st, dev);
+	if (ret)
+		return ret;
+
+	if (device_property_read_bool(dev, "adi,power-good-reset-on-fet")) {
+		ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1,
+					LTC4283_PWRGD_RST_CTRL_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,fet-turn-off-disable")) {
+		ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1,
+					LTC4283_FET_BAD_OFF_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,tmr-pull-down-disable")) {
+		ret = regmap_set_bits(st->map, LTC4283_CONTROL_1,
+				      LTC4283_THERM_TMR_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,dvdt-inrush-control-disable")) {
+		ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1,
+					LTC4283_DVDT_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) {
+		ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2,
+					LTC4283_UV_RETRY_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) {
+		ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2,
+					LTC4283_OV_RETRY_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,external-fault-retry-enable")) {
+		if (!st->ext_fault)
+			return dev_err_probe(dev, -EINVAL,
+					     "adi,external-fault-retry-enable set but PGIO4 not configured\n");
+		ret = regmap_set_bits(st->map, LTC4283_CONTROL_2,
+				      LTC4283_EXT_FAULT_RETRY_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,fault-log-enable")) {
+		ret = regmap_set_bits(st->map, LTC4283_FAULT_LOG_CTRL,
+				      LTC4283_FAULT_LOG_EN_MASK);
+		if (ret)
+			return ret;
+	}
+
+	ret = device_property_match_property_string(dev, "adi,overcurrent-retries",
+						    ltc4283_oc_fet_retry,
+						    ARRAY_SIZE(ltc4283_oc_fet_retry));
+	/* We still want to catch when an invalid string is given. */
+	if (ret != -EINVAL)
+		return dev_err_probe(dev, ret,
+				     "adi,overcurrent-retries invalid value\n");
+	if (ret >= 0) {
+		ret = regmap_update_bits(st->map, LTC4283_CONTROL_2,
+					 LTC4283_OC_RETRY_MASK,
+					 FIELD_PREP(LTC4283_OC_RETRY_MASK, ret));
+		if (ret)
+			return ret;
+	}
+
+	ret = device_property_match_property_string(dev, "adi,fet-bad-retries",
+						    ltc4283_oc_fet_retry,
+						    ARRAY_SIZE(ltc4283_oc_fet_retry));
+	if (ret != -EINVAL)
+		return dev_err_probe(dev, ret,
+				     "adi,fet-bad-retries invalid value\n");
+	if (ret >= 0) {
+		ret = regmap_update_bits(st->map, LTC4283_CONTROL_2,
+					 LTC4283_FET_BAD_RETRY_MASK,
+					 FIELD_PREP(LTC4283_FET_BAD_RETRY_MASK, ret));
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,external-fault-fet-off-enable")) {
+		if (!st->ext_fault)
+			return dev_err_probe(dev, -EINVAL,
+					     "adi,external-fault-fet-off-enable set but PGIO4 not configured\n");
+		ret = regmap_set_bits(st->map, LTC4283_CONFIG_3,
+				      LTC4283_EXTFLT_TURN_OFF_MASK);
+		if (ret)
+			return ret;
+	}
+
+	if (device_property_read_bool(dev, "adi,vpower-drns-enable")) {
+		__clear_bit(LTC4283_CHAN_DRAIN, &st->ch_enable_mask);
+		chan = LTC4283_CHAN_DRAIN - LTC4283_CHAN_ADI_1;
+		val = 1;
+	} else {
+		__clear_bit(LTC4283_CHAN_DRNS, &st->ch_enable_mask);
+		chan = LTC4283_CHAN_DRNS - LTC4283_CHAN_ADI_1;
+		val = 0;
+	}
+	/*
+	 * Then, let's by default disable the channel from the ADC2 that is
+	 * already being monitored by the VPWR channel. One can still enable it
+	 * later on if needed.
+	 */
+	ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(chan),
+				LTC4283_ADC_SELECT_MASK(chan));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(st->map, LTC4283_CONFIG_3,
+				 LTC4283_VPWR_DRNS_MASK,
+				 FIELD_PREP(LTC4283_VPWR_DRNS_MASK, val));
+	if (ret)
+		return ret;
+
+	/* Make sure the ADC has 12bit resolution since we're assuming that. */
+	ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG_2,
+				 LTC4283_ADC_MASK,
+				 FIELD_PREP(LTC4283_ADC_MASK, 3));
+	if (ret)
+		return ret;
+
+	/*
+	 * Make sure we are integrating power as we only support reporting
+	 * consumed energy.
+	 */
+	return regmap_clear_bits(st->map, LTC4283_METER_CONTROL,
+				 LTC4283_INTEGRATE_I_MASK);
+}
+
+static const struct hwmon_channel_info * const ltc4283_info[] = {
+	HWMON_CHANNEL_INFO(in,
+			   HWMON_I_LCRIT_ALARM | HWMON_I_CRIT_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_MAX_ALARM | HWMON_I_RESET_HISTORY |
+			   HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_FAULT | HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL,
+			   HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST |
+			   HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM |
+			   HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM |
+			   HWMON_I_ENABLE | HWMON_I_LABEL),
+	HWMON_CHANNEL_INFO(curr,
+			   HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST |
+			   HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM |
+			   HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM |
+			   HWMON_C_RESET_HISTORY | HWMON_C_LABEL),
+	HWMON_CHANNEL_INFO(power,
+			   HWMON_P_INPUT | HWMON_P_INPUT_LOWEST |
+			   HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN |
+			   HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM |
+			   HWMON_P_RESET_HISTORY | HWMON_P_LABEL),
+	HWMON_CHANNEL_INFO(energy,
+			   HWMON_E_ENABLE),
+	HWMON_CHANNEL_INFO(energy64,
+			   HWMON_E_INPUT),
+	NULL
+};
+
+static const struct hwmon_ops ltc4283_ops = {
+	.read = ltc4283_read,
+	.write = ltc4283_write,
+	.is_visible = ltc4283_is_visible,
+	.read_string = ltc4283_read_labels,
+};
+
+static const struct hwmon_chip_info ltc4283_chip_info = {
+	.ops = &ltc4283_ops,
+	.info = ltc4283_info,
+};
+
+static int ltc4283_show_fault_log(void *arg, u64 *val, u32 mask)
+{
+	struct ltc4283_hwmon *st = arg;
+	long alarm;
+	int ret;
+
+	ret = ltc4283_read_alarm(st, LTC4283_FAULT_LOG, mask, &alarm);
+	if (ret)
+		return ret;
+
+	*val = alarm;
+
+	return 0;
+}
+
+static int ltc4283_show_in0_lcrit_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_UV_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_lcrit_fault_log,
+			 ltc4283_show_in0_lcrit_fault_log, NULL, "%llu\n");
+
+static int ltc4283_show_in0_crit_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_OV_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_crit_fault_log,
+			 ltc4283_show_in0_crit_fault_log, NULL, "%llu\n");
+
+static int ltc4283_show_fet_bad_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_FET_BAD_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_bad_fault_log,
+			 ltc4283_show_fet_bad_fault_log, NULL, "%llu\n");
+
+static int ltc4283_show_fet_short_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_FET_SHORT_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_short_fault_log,
+			 ltc4283_show_fet_short_fault_log, NULL, "%llu\n");
+
+static int ltc4283_show_curr1_crit_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_OC_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_curr1_crit_fault_log,
+			 ltc4283_show_curr1_crit_fault_log, NULL, "%llu\n");
+
+static int ltc4283_show_power1_failed_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_PWR_FAIL_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_failed_fault_log,
+			 ltc4283_show_power1_failed_fault_log, NULL, "%llu\n");
+
+static int ltc4283_show_power1_good_input_fault_log(void *arg, u64 *val)
+{
+	return ltc4283_show_fault_log(arg, val, LTC4283_PGI_FAULT_MASK);
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_good_input_fault_log,
+			 ltc4283_show_power1_good_input_fault_log, NULL, "%llu\n");
+
+static void ltc4283_debugfs_init(struct ltc4283_hwmon *st, struct i2c_client *i2c)
+{
+	debugfs_create_file_unsafe("in0_crit_fault_log", 0400, i2c->debugfs, st,
+				   &ltc4283_in0_crit_fault_log);
+	debugfs_create_file_unsafe("in0_lcrit_fault_log", 0400, i2c->debugfs, st,
+				   &ltc4283_in0_lcrit_fault_log);
+	debugfs_create_file_unsafe("in0_fet_bad_fault_log", 0400, i2c->debugfs, st,
+				   &ltc4283_fet_bad_fault_log);
+	debugfs_create_file_unsafe("in0_fet_short_fault_log", 0400, i2c->debugfs, st,
+				   &ltc4283_fet_short_fault_log);
+	debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st,
+				   &ltc4283_curr1_crit_fault_log);
+	debugfs_create_file_unsafe("power1_failed_fault_log", 0400, i2c->debugfs, st,
+				   &ltc4283_power1_failed_fault_log);
+	debugfs_create_file_unsafe("power1_good_input_fault_log", 0400, i2c->debugfs,
+				   st, &ltc4283_power1_good_input_fault_log);
+}
+
+static bool ltc4283_word_reg(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case LTC4283_SENSE ... LTC4283_ADIO34_MAX:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static const struct regmap_config ltc4283_word_regmap_config = {
+	.name = "ltc4283-16",
+	.reg_bits = 8,
+	.val_bits = 16,
+	.max_register = LTC4283_ADIO34_MAX,
+	.val_format_endian = REGMAP_ENDIAN_BIG,
+	.writeable_reg = ltc4283_word_reg,
+	.readable_reg = ltc4283_word_reg,
+};
+
+static bool ltc4283_writable_reg(struct device *dev, unsigned int reg)
+{
+	if (ltc4283_word_reg(dev, reg))
+		return false;
+
+	switch (reg) {
+	case LTC4283_SYSTEM_STATUS ... LTC4283_FAULT_STATUS:
+		return false;
+	case LTC4283_RESERVED_OC:
+		return false;
+	case LTC4283_RESERVED_86 ... LTC4283_RESERVED_8F:
+		return false;
+	case LTC4283_RESERVED_91 ... LTC4283_RESERVED_A1:
+		return false;
+	case LTC4283_RESERVED_A3:
+		return false;
+	case LTC4283_RESERVED_AC:
+		return false;
+	case LTC4283_POWER_PLAY_MSB ... LTC4283_POWER_PLAY_LSB:
+		return false;
+	case LTC4283_RESERVED_F1 ... LTC4283_RESERVED_FF:
+		return false;
+	default:
+		return true;
+	}
+}
+
+static bool ltc4283_readable_reg(struct device *dev, unsigned int reg)
+{
+	if (ltc4283_word_reg(dev, reg))
+		return false;
+
+	return true;
+}
+
+static const struct regmap_config ltc4283_regmap_config = {
+	.name = "ltc4283-8",
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = 0xff,
+	.writeable_reg = ltc4283_writable_reg,
+	.readable_reg = ltc4283_readable_reg,
+};
+
+static int ltc4283_probe(struct i2c_client *client)
+{
+	struct device *dev = &client->dev, *hwmon;
+	struct auxiliary_device *adev;
+	struct ltc4283_hwmon *st;
+	int ret;
+
+	st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
+	if (!st)
+		return -ENOMEM;
+
+	st->map = devm_regmap_init_i2c(client, &ltc4283_regmap_config);
+	if (IS_ERR(st->map))
+		return dev_err_probe(dev, PTR_ERR(st->map),
+				     "Failed to create regmap\n");
+
+	st->map_word = devm_regmap_init_i2c(client, &ltc4283_word_regmap_config);
+	if (IS_ERR(st->map_word))
+		return dev_err_probe(dev, PTR_ERR(st->map_word),
+				     "Failed to create word regmap\n");
+
+	ret = ltc4283_setup(st, dev);
+	if (ret)
+		return ret;
+
+	hwmon = devm_hwmon_device_register_with_info(dev, "ltc4283", st,
+						     &ltc4283_chip_info, NULL);
+
+	if (IS_ERR(hwmon))
+		return PTR_ERR(hwmon);
+
+	ltc4283_debugfs_init(st, client);
+
+	if (!st->gpio_mask)
+		return 0;
+
+	adev = devm_auxiliary_device_create(dev, "gpio", &st->gpio_mask);
+	if (!adev)
+		return dev_err_probe(dev, -ENODEV, "Failed to add GPIO device\n");
+
+	return 0;
+}
+
+static const struct of_device_id ltc4283_of_match[] = {
+	{ .compatible = "adi,ltc4283" },
+	{ }
+};
+
+static const struct i2c_device_id ltc4283_i2c_id[] = {
+	{ "ltc4283" },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, ltc4283_i2c_id);
+
+static struct i2c_driver ltc4283_driver = {
+	.driver	= {
+		.name = "ltc4283",
+		.of_match_table = ltc4283_of_match,
+	},
+	.probe = ltc4283_probe,
+	.id_table = ltc4283_i2c_id,
+};
+module_i2c_driver(ltc4283_driver);
+
+MODULE_AUTHOR("Nuno Sá <nuno.sa@analog.com>");
+MODULE_DESCRIPTION("LTC4283 How Swap Controller driver");
+MODULE_LICENSE("GPL");

-- 
2.52.0

[PATCH v5 3/3] gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller

[Nuno Sá via B4 Relay]

From: Nuno Sá <nuno.sa@analog.com>

The LTC4283 device has up to 8 pins that can be configured as GPIOs.

Note that PGIO pins are not set as GPIOs by default so if they are
configured to be used as GPIOs we need to make sure to initialize them
to a sane default. They are set as inputs by default.

Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Nuno Sá <nuno.sa@analog.com>
---
 MAINTAINERS                 |   2 +
 drivers/gpio/Kconfig        |  15 +++
 drivers/gpio/Makefile       |   1 +
 drivers/gpio/gpio-ltc4283.c | 218 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 236 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9fa27d0b1890..4d544996fde8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14957,9 +14957,11 @@ F:	drivers/hwmon/ltc4282.c
 
 LTC4283 HARDWARE MONITOR AND GPIO DRIVER
 M:	Nuno Sá <nuno.sa@analog.com>
+L:	linux-gpio@vger.kernel.org
 L:	linux-hwmon@vger.kernel.org
 S:	Supported
 F:	Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml
+F:	drivers/gpio/gpio-ltc4283.c
 F:	drivers/hwmon/ltc4283.c
 
 LTC4286 HARDWARE MONITOR DRIVER
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c74da29253e8..5dc603268a75 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1749,6 +1749,21 @@ config GPIO_WM8994
 
 endmenu
 
+menu "Auxiliary Bus GPIO drivers"
+	depends on AUXILIARY_BUS
+
+config GPIO_LTC4283
+	tristate "Analog Devices LTC4283 GPIO support"
+	depends on SENSORS_LTC4283
+	help
+	  If you say yes here you want the GPIO function available in Analog
+	  Devices LTC4283 Negative Voltage Hot Swap Controller.
+
+	  This driver can also be built as a module. If so, the module will
+	  be called gpio-ltc4283.
+
+endmenu
+
 menu "PCI GPIO expanders"
 	depends on PCI
 
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 2421a8fd3733..f38e529f4618 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_GPIO_LP873X)		+= gpio-lp873x.o
 obj-$(CONFIG_GPIO_LP87565)		+= gpio-lp87565.o
 obj-$(CONFIG_GPIO_LPC18XX)		+= gpio-lpc18xx.o
 obj-$(CONFIG_GPIO_LPC32XX)		+= gpio-lpc32xx.o
+obj-$(CONFIG_GPIO_LTC4283)		+= gpio-ltc4283.o
 obj-$(CONFIG_GPIO_MACSMC)		+= gpio-macsmc.o
 obj-$(CONFIG_GPIO_MADERA)		+= gpio-madera.o
 obj-$(CONFIG_GPIO_MAX3191X)		+= gpio-max3191x.o
diff --git a/drivers/gpio/gpio-ltc4283.c b/drivers/gpio/gpio-ltc4283.c
new file mode 100644
index 000000000000..fa0c106d4fac
--- /dev/null
+++ b/drivers/gpio/gpio-ltc4283.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Analog Devices LTC4283 GPIO driver
+ *
+ * Copyright 2025 Analog Devices Inc.
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/bitfield.h>
+#include <linux/bitmap.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/gpio/driver.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#define LTC4283_PINS_MAX			8
+#define LTC4283_PGIOX_START_NR			4
+#define LTC4283_INPUT_STATUS			0x02
+#define LTC4283_PGIO_CONFIG			0x10
+#define   LTC4283_PGIO_CFG_MASK(pin) \
+	GENMASK(((pin) - LTC4283_PGIOX_START_NR) * 2 + 1, (((pin) - LTC4283_PGIOX_START_NR) * 2))
+#define LTC4283_PGIO_CONFIG_2			0x11
+
+#define LTC42823_ADIO_CONFIG			0x12
+/* starts at bit 4 */
+#define   LTC4283_ADIOX_CONFIG_MASK(pin)	BIT((pin) + 4)
+#define LTC4283_PGIO_DIR_IN			3
+#define LTC4283_PGIO_DIR_OUT			2
+
+struct ltc4283_gpio {
+	struct gpio_chip gpio_chip;
+	struct regmap *regmap;
+};
+
+static int ltc4283_pgio_get_direction(const struct ltc4283_gpio *st, unsigned int off)
+{
+	unsigned int val;
+	int ret;
+
+	ret = regmap_read(st->regmap, LTC4283_PGIO_CONFIG, &val);
+	if (ret)
+		return ret;
+
+	val = field_get(LTC4283_PGIO_CFG_MASK(off), val);
+	if (val == LTC4283_PGIO_DIR_IN)
+		return GPIO_LINE_DIRECTION_IN;
+
+	return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int ltc4283_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
+{
+	struct ltc4283_gpio *st = gpiochip_get_data(gc);
+	unsigned int val;
+	int ret;
+
+	if (off >= LTC4283_PGIOX_START_NR)
+		return ltc4283_pgio_get_direction(st, off);
+
+	ret = regmap_read(st->regmap, LTC42823_ADIO_CONFIG, &val);
+	if (ret)
+		return ret;
+
+	if (val & LTC4283_ADIOX_CONFIG_MASK(off))
+		return GPIO_LINE_DIRECTION_IN;
+
+	return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int ltc4283_gpio_direction_set(const struct ltc4283_gpio *st,
+				      unsigned int off, bool input)
+{
+	if (off >= LTC4283_PGIOX_START_NR) {
+		unsigned int val = LTC4283_PGIO_DIR_OUT;
+
+		if (input)
+			val = LTC4283_PGIO_DIR_IN;
+
+		val = field_prep(LTC4283_PGIO_CFG_MASK(off), val);
+		return regmap_update_bits(st->regmap, LTC4283_PGIO_CONFIG,
+					  LTC4283_PGIO_CFG_MASK(off), val);
+	}
+
+	return regmap_update_bits(st->regmap, LTC42823_ADIO_CONFIG,
+				  LTC4283_ADIOX_CONFIG_MASK(off),
+				  field_prep(LTC4283_ADIOX_CONFIG_MASK(off), input));
+}
+
+static int __ltc4283_gpio_set_value(const struct ltc4283_gpio *st,
+				    unsigned int off, int val)
+{
+	u32 reg = off < LTC4283_PGIOX_START_NR ? LTC42823_ADIO_CONFIG : LTC4283_PGIO_CONFIG_2;
+
+	return regmap_update_bits(st->regmap, reg, BIT(off),
+				  field_prep(BIT(off), !!val));
+}
+
+static int ltc4283_gpio_direction_input(struct gpio_chip *gc, unsigned int off)
+{
+	struct ltc4283_gpio *st = gpiochip_get_data(gc);
+
+	return ltc4283_gpio_direction_set(st, off, true);
+}
+
+static int ltc4283_gpio_direction_output(struct gpio_chip *gc, unsigned int off, int val)
+{
+	struct ltc4283_gpio *st = gpiochip_get_data(gc);
+	int ret;
+
+	ret = ltc4283_gpio_direction_set(st, off, false);
+	if (ret)
+		return ret;
+
+	return __ltc4283_gpio_set_value(st, off, val);
+}
+
+static int ltc4283_gpio_get_value(struct gpio_chip *gc, unsigned int off)
+{
+	struct ltc4283_gpio *st = gpiochip_get_data(gc);
+	unsigned int val, reg;
+	int ret, dir;
+
+	dir = ltc4283_gpio_get_direction(gc, off);
+	if (dir < 0)
+		return dir;
+
+	if (dir == GPIO_LINE_DIRECTION_IN) {
+		ret = regmap_read(st->regmap, LTC4283_INPUT_STATUS, &val);
+		if (ret)
+			return ret;
+
+		/* ADIO1 is at bit 3. */
+		if (off < LTC4283_PGIOX_START_NR)
+			return !!(val & BIT(3 - off));
+
+		/* PGIO1 is at bit 7. */
+		return !!(val & BIT(7 - (off - LTC4283_PGIOX_START_NR)));
+	}
+
+	if (off < LTC4283_PGIOX_START_NR)
+		reg = LTC42823_ADIO_CONFIG;
+	else
+		reg = LTC4283_PGIO_CONFIG_2;
+
+	ret = regmap_read(st->regmap, reg, &val);
+	if (ret)
+		return ret;
+
+	return !!(val & BIT(off));
+}
+
+static int ltc4283_gpio_set_value(struct gpio_chip *gc, unsigned int off, int val)
+{
+	struct ltc4283_gpio *st = gpiochip_get_data(gc);
+
+	return __ltc4283_gpio_set_value(st, off, val);
+}
+
+static int ltc4283_init_valid_mask(struct gpio_chip *gc, unsigned long *valid_mask,
+				   unsigned int ngpios)
+{
+	unsigned long *mask = dev_get_platdata(gc->parent);
+
+	bitmap_copy(valid_mask, mask, ngpios);
+	return 0;
+}
+
+static int ltc4283_gpio_probe(struct auxiliary_device *adev,
+			      const struct auxiliary_device_id *id)
+{
+	struct device *dev = &adev->dev;
+	struct ltc4283_gpio *st;
+	struct gpio_chip *gc;
+
+	st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
+	if (!st)
+		return -ENOMEM;
+
+	st->regmap = dev_get_regmap(dev->parent, "ltc4283-8");
+	if (!st->regmap)
+		return dev_err_probe(dev, -ENODEV,
+				     "Failed to get byte regmap\n");
+
+	gc = &st->gpio_chip;
+	gc->parent = dev;
+	gc->get_direction = ltc4283_gpio_get_direction;
+	gc->direction_input = ltc4283_gpio_direction_input;
+	gc->direction_output = ltc4283_gpio_direction_output;
+	gc->get = ltc4283_gpio_get_value;
+	gc->set = ltc4283_gpio_set_value;
+	gc->init_valid_mask = ltc4283_init_valid_mask;
+	gc->can_sleep = true;
+
+	gc->base = -1;
+	gc->ngpio = LTC4283_PINS_MAX;
+	gc->label = adev->name;
+	gc->owner = THIS_MODULE;
+
+	return devm_gpiochip_add_data(dev, &st->gpio_chip, st);
+}
+
+static const struct auxiliary_device_id ltc4283_aux_id_table[] = {
+	{ "ltc4283.gpio" },
+	{ }
+};
+MODULE_DEVICE_TABLE(auxiliary, ltc4283_aux_id_table);
+
+static struct auxiliary_driver ltc4283_gpio_driver = {
+	.probe = ltc4283_gpio_probe,
+	.id_table = ltc4283_aux_id_table,
+};
+module_auxiliary_driver(ltc4283_gpio_driver);
+
+MODULE_AUTHOR("Nuno Sá <nuno.sa@analog.com>");
+MODULE_DESCRIPTION("GPIO LTC4283 Driver");
+MODULE_LICENSE("GPL");

-- 
2.52.0

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

Hi Nuno,

On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> This is v3 for the LTC4283 how swap controller. Main change is that I'm
> now using the auxiliary bus for adding the GPIO device (done depending
> on FW properties).
> 
> Similar to the LTC4282 device, we're clearing some fault logs in the
> reset_history attributes.
> 
> Guenter, in [1] you can find some replies for some questions you had in
> v2 that likely you don't remember anymore. Regarding the regmap story I
> ended up adding a secong regmap for the 16 bit wide registers which
> seems like a clean solution (if I'm not missing nothing).
> 

Sorry for the long delay.

Actually I prefer the solution used in the lm75 driver: Map all registers
to 16-bit registers using a regmap bus. Would that be possible ?

Other than that, I ran the series through an AI review. This is what it told me:

   Identified Violations and Observations:

    * Alphabetical Order of Includes: In drivers/hwmon/ltc4283.c, the include files are not strictly in alphabetical order.
        * #include <linux/hwmon.h> is listed before #include <linux/hwmon-sysfs.h>.

-> Actually, linux/hwmon-sysfs.h> does not have to be included in the first place.

        * According to strict ASCII sorting (e.g., LC_ALL=C sort), hwmon-sysfs.h should come first because the hyphen - (ASCII 45) precedes the dot . (ASCII 46).
    * Documentation Discrepancy: The file Documentation/hwmon/ltc4283.rst includes a section for "Addresses scanned" listing I2C addresses 0x10-0x17 and 0x20-0x2E.
        * Inaccuracy: The driver does not implement a .detect function, meaning no I2C address scanning is actually performed.
        * Guideline Violation: The submitting-patches.rst guideline states that only specific I2C addresses (0x18-0x1f, 0x28-0x2f, etc.) shall be probed. The addresses listed in the documentation (specifically 0x10-0x17) are outside of this
          approved range. While the driver doesn't probe, the documentation misleadingly suggests it does so on non-approved addresses.

-> Please fix.

Thanks,
Guenter

> [1]: https://lore.kernel.org/linux-hwmon/0765a0b89779331c62a3f136ef030f7f2f40ea47.camel@gmail.com/
> [2]: https://lore.kernel.org/linux-iio/cover.1761588465.git.geert+renesas@glider.be/
> 
> ---
> Changes in v5:
> - Patch 2:
>    * Added a secong regmap for the 16bit wide registers;
>    * Add default value for rsense so that we can probe without FW
>      properties;
>    * Make sure to give the right file permissions to the reset_history
>      attrs.
> - Patch 3:
>    * Make sure to get the right regmap (given that the device now has 2);
>    * Add error handling for getting the regmap.
> - Link to v4: https://lore.kernel.org/r/20251204-ltc4283-support-v4-0-db0197fd7984@analog.com
> 
> ---
> Nuno Sá (3):
>        dt-bindings: hwmon: Document the LTC4283 Swap Controller
>        hwmon: ltc4283: Add support for the LTC4283 Swap Controller
>        gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller
> 
>   .../devicetree/bindings/hwmon/adi,ltc4283.yaml     |  272 +++
>   Documentation/hwmon/index.rst                      |    1 +
>   Documentation/hwmon/ltc4283.rst                    |  266 +++
>   MAINTAINERS                                        |    9 +
>   drivers/gpio/Kconfig                               |   15 +
>   drivers/gpio/Makefile                              |    1 +
>   drivers/gpio/gpio-ltc4283.c                        |  218 +++
>   drivers/hwmon/Kconfig                              |   12 +
>   drivers/hwmon/Makefile                             |    1 +
>   drivers/hwmon/ltc4283.c                            | 1766 ++++++++++++++++++++
>   10 files changed, 2561 insertions(+)
> ---
> base-commit: bc04acf4aeca588496124a6cf54bfce3db327039
> change-id: 20250812-ltc4283-support-27c8c4e69c6b
> --
> 
> Thanks!
> - Nuno Sá
> 
> 
> 

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Nuno Sá]

On Sat, 2026-01-17 at 16:27 -0800, Guenter Roeck wrote:
> Hi Nuno,
> 
> On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> > This is v3 for the LTC4283 how swap controller. Main change is that I'm
> > now using the auxiliary bus for adding the GPIO device (done depending
> > on FW properties).
> > 
> > Similar to the LTC4282 device, we're clearing some fault logs in the
> > reset_history attributes.
> > 
> > Guenter, in [1] you can find some replies for some questions you had in
> > v2 that likely you don't remember anymore. Regarding the regmap story I
> > ended up adding a secong regmap for the 16 bit wide registers which
> > seems like a clean solution (if I'm not missing nothing).
> > 
> 
> Sorry for the long delay.
> 
> Actually I prefer the solution used in the lm75 driver: Map all registers
> to 16-bit registers using a regmap bus. Would that be possible ?

I do like the current approach as we get the proper i2c functionality checks from
regmap and it actually maps the device register layout. But no strong feeling so
obvioulsy I'll try the lm75 way. However looking at code, something come to mind.
Won't the below break on big endian machines (assuming big endian device)?

https://elixir.bootlin.com/linux/v6.19-rc4/source/drivers/hwmon/lm75.c#L594

Sunday morning for me so I might be missing something :). FWIW, if I'ḿ right about
the above, then regmap i2c has the same issue (tough the issue seems to be on the i2c
API - at first glance).

Will also look at the below feedback.

Thanks!
- Nuno Sá

> 
> Other than that, I ran the series through an AI review. This is what it told me:
> 
>    Identified Violations and Observations:
> 
>     * Alphabetical Order of Includes: In drivers/hwmon/ltc4283.c, the include files
> are not strictly in alphabetical order.
>         * #include <linux/hwmon.h> is listed before #include <linux/hwmon-sysfs.h>.
> 
> -> Actually, linux/hwmon-sysfs.h> does not have to be included in the first place.
> 
>         * According to strict ASCII sorting (e.g., LC_ALL=C sort), hwmon-sysfs.h
> should come first because the hyphen - (ASCII 45) precedes the dot . (ASCII 46).
>     * Documentation Discrepancy: The file Documentation/hwmon/ltc4283.rst includes
> a section for "Addresses scanned" listing I2C addresses 0x10-0x17 and 0x20-0x2E.
>         * Inaccuracy: The driver does not implement a .detect function, meaning no
> I2C address scanning is actually performed.
>         * Guideline Violation: The submitting-patches.rst guideline states that
> only specific I2C addresses (0x18-0x1f, 0x28-0x2f, etc.) shall be probed. The
> addresses listed in the documentation (specifically 0x10-0x17) are outside of this
>           approved range. While the driver doesn't probe, the documentation
> misleadingly suggests it does so on non-approved addresses.
> 
> -> Please fix.
> 
> Thanks,
> Guenter
> 
> > [1]:
> > https://lore.kernel.org/linux-hwmon/0765a0b89779331c62a3f136ef030f7f2f40ea47.camel@gmail.com/
> > [2]:
> > https://lore.kernel.org/linux-iio/cover.1761588465.git.geert+renesas@glider.be/
> > 
> > ---
> > Changes in v5:
> > - Patch 2:
> >    * Added a secong regmap for the 16bit wide registers;
> >    * Add default value for rsense so that we can probe without FW
> >      properties;
> >    * Make sure to give the right file permissions to the reset_history
> >      attrs.
> > - Patch 3:
> >    * Make sure to get the right regmap (given that the device now has 2);
> >    * Add error handling for getting the regmap.
> > - Link to v4:
> > https://lore.kernel.org/r/20251204-ltc4283-support-v4-0-db0197fd7984@analog.com
> > 
> > ---
> > Nuno Sá (3):
> >        dt-bindings: hwmon: Document the LTC4283 Swap Controller
> >        hwmon: ltc4283: Add support for the LTC4283 Swap Controller
> >        gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller
> > 
> >   .../devicetree/bindings/hwmon/adi,ltc4283.yaml     |  272 +++
> >   Documentation/hwmon/index.rst                      |    1 +
> >   Documentation/hwmon/ltc4283.rst                    |  266 +++
> >   MAINTAINERS                                        |    9 +
> >   drivers/gpio/Kconfig                               |   15 +
> >   drivers/gpio/Makefile                              |    1 +
> >   drivers/gpio/gpio-ltc4283.c                        |  218 +++
> >   drivers/hwmon/Kconfig                              |   12 +
> >   drivers/hwmon/Makefile                             |    1 +
> >   drivers/hwmon/ltc4283.c                            | 1766 ++++++++++++++++++++
> >   10 files changed, 2561 insertions(+)
> > ---
> > base-commit: bc04acf4aeca588496124a6cf54bfce3db327039
> > change-id: 20250812-ltc4283-support-27c8c4e69c6b
> > --
> > 
> > Thanks!
> > - Nuno Sá
> > 
> > 
> > 

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

On 1/18/26 02:12, Nuno Sá wrote:
> On Sat, 2026-01-17 at 16:27 -0800, Guenter Roeck wrote:
>> Hi Nuno,
>>
>> On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
>>> This is v3 for the LTC4283 how swap controller. Main change is that I'm
>>> now using the auxiliary bus for adding the GPIO device (done depending
>>> on FW properties).
>>>
>>> Similar to the LTC4282 device, we're clearing some fault logs in the
>>> reset_history attributes.
>>>
>>> Guenter, in [1] you can find some replies for some questions you had in
>>> v2 that likely you don't remember anymore. Regarding the regmap story I
>>> ended up adding a secong regmap for the 16 bit wide registers which
>>> seems like a clean solution (if I'm not missing nothing).
>>>
>>
>> Sorry for the long delay.
>>
>> Actually I prefer the solution used in the lm75 driver: Map all registers
>> to 16-bit registers using a regmap bus. Would that be possible ?
> 
> I do like the current approach as we get the proper i2c functionality checks from
> regmap and it actually maps the device register layout. But no strong feeling so
> obvioulsy I'll try the lm75 way. However looking at code, something come to mind.
> Won't the below break on big endian machines (assuming big endian device)?
> 
> https://elixir.bootlin.com/linux/v6.19-rc4/source/drivers/hwmon/lm75.c#L594
> 
> Sunday morning for me so I might be missing something :). FWIW, if I'ḿ right about
> the above, then regmap i2c has the same issue (tough the issue seems to be on the i2c
> API - at first glance).
> 

Technically possible, but the driver used i2c_smbus_{read,write}_word_swapped
since 2011 (even in pre-regmap times). Before that it used essentially the
same code (i2c_smbus_read_word_data followed by swab16), only it was hand-coded.
I would assume that someone would have noticed that problem in all that time.

Guenter

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Nuno Sá]

On Sat, 2026-01-17 at 16:27 -0800, Guenter Roeck wrote:
> Hi Nuno,
> 
> On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> > This is v3 for the LTC4283 how swap controller. Main change is that I'm
> > now using the auxiliary bus for adding the GPIO device (done depending
> > on FW properties).
> > 
> > Similar to the LTC4282 device, we're clearing some fault logs in the
> > reset_history attributes.
> > 
> > Guenter, in [1] you can find some replies for some questions you had in
> > v2 that likely you don't remember anymore. Regarding the regmap story I
> > ended up adding a secong regmap for the 16 bit wide registers which
> > seems like a clean solution (if I'm not missing nothing).
> > 
> 
> Sorry for the long delay.
> 
> Actually I prefer the solution used in the lm75 driver: Map all registers
> to 16-bit registers using a regmap bus. Would that be possible ?

Hi Guenter,

I intend to send the next iteration by the end of the week (finally!) but there's something
I wanted to know if you have any strong opinion on.

So, the above is a bit annoying because of the energy reading which is 6 bytes long (so, 6 regmap
reads). Given that our custom bus will now have val_bits = 16 that won't work out of the box. So:

1. Either I directly use the i2c block API to get the 6 bytes.
2. Or I use regmap_bulk_read() with val_count of 3.

I don't like much of mixing regmap with "plain" bus calls but given it's only in one place, might
not be that bad. OTOH, to use regmap I do need to account for it (and yet another corner case) in
the read callback (so I do not use the i2c swapped version for the energy reading).

I do not have any strong opinion but I'm more tempted in going with 1.

- Nuno Sá
> 

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

On 2/17/26 05:39, Nuno Sá wrote:
> On Sat, 2026-01-17 at 16:27 -0800, Guenter Roeck wrote:
>> Hi Nuno,
>>
>> On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
>>> This is v3 for the LTC4283 how swap controller. Main change is that I'm
>>> now using the auxiliary bus for adding the GPIO device (done depending
>>> on FW properties).
>>>
>>> Similar to the LTC4282 device, we're clearing some fault logs in the
>>> reset_history attributes.
>>>
>>> Guenter, in [1] you can find some replies for some questions you had in
>>> v2 that likely you don't remember anymore. Regarding the regmap story I
>>> ended up adding a secong regmap for the 16 bit wide registers which
>>> seems like a clean solution (if I'm not missing nothing).
>>>
>>
>> Sorry for the long delay.
>>
>> Actually I prefer the solution used in the lm75 driver: Map all registers
>> to 16-bit registers using a regmap bus. Would that be possible ?
> 
> Hi Guenter,
> 
> I intend to send the next iteration by the end of the week (finally!) but there's something
> I wanted to know if you have any strong opinion on.
> 
> So, the above is a bit annoying because of the energy reading which is 6 bytes long (so, 6 regmap
> reads). Given that our custom bus will now have val_bits = 16 that won't work out of the box. So:
> 
> 1. Either I directly use the i2c block API to get the 6 bytes.
> 2. Or I use regmap_bulk_read() with val_count of 3.
> 
> I don't like much of mixing regmap with "plain" bus calls but given it's only in one place, might
> not be that bad. OTOH, to use regmap I do need to account for it (and yet another corner case) in
> the read callback (so I do not use the i2c swapped version for the energy reading).
> 
> I do not have any strong opinion but I'm more tempted in going with 1.
> 

Sorry, this got lost. I think 1 is the better choice here. This is really a messy chip :-(.

Guenter

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

Hi Nuno,

On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> This is v3 for the LTC4283 how swap controller. Main change is that I'm
> now using the auxiliary bus for adding the GPIO device (done depending
> on FW properties).
> 
> Similar to the LTC4282 device, we're clearing some fault logs in the
> reset_history attributes.
> 

I ran the patch series through an AI review. Results are below.
Please take a look.

Thanks,
Guenter

---
# Deep Dive Regression Analysis Log
Date: 2026-01-27

## Commit 5998c620fbd8: gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller

**Context**:
- Adds a new GPIO driver `drivers/gpio/gpio-ltc4283.c`.
- Depends on `drivers/hwmon/ltc4283.c` for regmap and MFD instantiation.

**Findings**:
1.  **Typo/Naming Issue**:
     - File `drivers/gpio/gpio-ltc4283.c` uses `LTC42823_ADIO_CONFIG` definition.
     - `LTC42823` appears to be a typo for `LTC4283`.
     - `drivers/gpio/gpio-ltc4283.c:26`: `#define LTC42823_ADIO_CONFIG 0x12`

2.  **Logic Verification**:
     - GPIO direction and value setting logic appears consistent with bitmasks provided, assuming register `0x12` and `0x11` layout is correct as inferred.

3.  **Regressions**:
     - No critical functional regressions found in this commit alone.
     - Code quality: Typo in macro name.

## Commit 82433332ce16: hwmon: ltc4283: Add support for the LTC4283 Swap Controller

**Context**:
- Adds core HWMON driver `drivers/hwmon/ltc4283.c`.
- Handles I2C communication, regmap initialization, and MFD child creation.

**Findings**:
1.  **Critical Regression: DebugFS Use-After-Free**:
     - `ltc4283_probe` calls `ltc4283_debugfs_init`.
     - `ltc4283_debugfs_init` calls `debugfs_create_file_unsafe` creating files associated with `st`.
     - `st` is allocated with `devm_kzalloc`.
     - **Issue**: There is no explicit cleanup of debugfs entries (e.g., `debugfs_remove_recursive`) and no `devm_add_action` to handle it.
     - **Consequence**: When the driver is unbound/unloaded, `st` is freed by devm. The debugfs entries remain. Accessing them triggers a Use-After-Free on `st`.
     - **Fix Required**: Use `devm_add_action_or_reset` to remove debugfs directory/entries on driver detach.

2.  **Typo**:
     - `drivers/hwmon/ltc4283.c:1765`: `MODULE_DESCRIPTION("LTC4283 How Swap Controller driver");`
     - "How Swap" should be "Hot Swap".

3.  **Property Handling**:
     - Driver respects "missing property" by keeping hardware/EEPROM defaults, while Bindings document specific defaults. This is a minor consistency issue but likely acceptable if EEPROM usually matches defaults.

## Commit a175d04e5900: dt-bindings: hwmon: Document the LTC4283 Swap Controller

**Context**:
- Adds DT bindings.

**Findings**:
- Bindings appear correct and consistent with driver usage.
- Dependencies logic (`adi,external-fault-retry-enable` requiring `adi,pgio4-func` to not be `gpio`) is enforced in both YAML and Driver.

## Summary

**Final Regressions Found**: 1 Major (DebugFS UAF), 2 Minor (Typos).

1.  **Major**: `drivers/hwmon/ltc4283.c`: DebugFS entries are not removed on driver unload, leading to UAF.
2.  **Minor**: `drivers/gpio/gpio-ltc4283.c`: `LTC42823_ADIO_CONFIG` typo.
3.  **Minor**: `drivers/hwmon/ltc4283.c`: `MODULE_DESCRIPTION` "How Swap" typo.

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Nuno Sá]

Hi Guenter,

On Tue, 2026-01-27 at 09:39 -0800, Guenter Roeck wrote:
> Hi Nuno,
> 
> On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> > This is v3 for the LTC4283 how swap controller. Main change is that I'm
> > now using the auxiliary bus for adding the GPIO device (done depending
> > on FW properties).
> > 
> > Similar to the LTC4282 device, we're clearing some fault logs in the
> > reset_history attributes.
> > 
> 
> I ran the patch series through an AI review. Results are below.
> Please take a look.
> 
> Thanks,
> Guenter
> 
> ---
> # Deep Dive Regression Analysis Log
> Date: 2026-01-27
> 
> ## Commit 5998c620fbd8: gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller
> 
> **Context**:
> - Adds a new GPIO driver `drivers/gpio/gpio-ltc4283.c`.
> - Depends on `drivers/hwmon/ltc4283.c` for regmap and MFD instantiation.
> 
> **Findings**:
> 1.  **Typo/Naming Issue**:
>      - File `drivers/gpio/gpio-ltc4283.c` uses `LTC42823_ADIO_CONFIG` definition.
>      - `LTC42823` appears to be a typo for `LTC4283`.
>      - `drivers/gpio/gpio-ltc4283.c:26`: `#define LTC42823_ADIO_CONFIG 0x12`
> 
> 2.  **Logic Verification**:
>      - GPIO direction and value setting logic appears consistent with bitmasks provided, assuming
> register `0x12` and `0x11` layout is correct as inferred.
> 
> 3.  **Regressions**:
>      - No critical functional regressions found in this commit alone.
>      - Code quality: Typo in macro name.
> 
> ## Commit 82433332ce16: hwmon: ltc4283: Add support for the LTC4283 Swap Controller
> 
> **Context**:
> - Adds core HWMON driver `drivers/hwmon/ltc4283.c`.
> - Handles I2C communication, regmap initialization, and MFD child creation.
> 
> **Findings**:
> 1.  **Critical Regression: DebugFS Use-After-Free**:
>      - `ltc4283_probe` calls `ltc4283_debugfs_init`.
>      - `ltc4283_debugfs_init` calls `debugfs_create_file_unsafe` creating files associated with
> `st`.
>      - `st` is allocated with `devm_kzalloc`.
>      - **Issue**: There is no explicit cleanup of debugfs entries (e.g.,
> `debugfs_remove_recursive`) and no `devm_add_action` to handle it.
>      - **Consequence**: When the driver is unbound/unloaded, `st` is freed by devm. The debugfs
> entries remain. Accessing them triggers a Use-After-Free on `st`.
>      - **Fix Required**: Use `devm_add_action_or_reset` to remove debugfs directory/entries on
> driver detach.

So actually a nice deduction from the agent but not accurate given that all the entries should be
removed in [1]. If you want it to be explicit, I can add the action but given that the dentry is
given by i2c, I would argue it's fair to assume i2c will take care of the removal. Thoughts?

I'm also planning to pick this up again but was caught by something else. So hopefully next week. 

On another topic, I also (you questioned it in another thread) looked around and I do have a ltc4282
board with me. Given that I just need to power up the digital parts to access the i2c bus, it should
be pretty straight to get a register dump. So if you're still interested on that, I should be able
to do it.

[1]: https://elixir.bootlin.com/linux/v6.19-rc5/source/drivers/i2c/i2c-core-base.c#L634

- Nuno Sá
> 

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

On 1/28/26 01:44, Nuno Sá wrote:
> Hi Guenter,
> 
> On Tue, 2026-01-27 at 09:39 -0800, Guenter Roeck wrote:
>> Hi Nuno,
>>
>> On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
>>> This is v3 for the LTC4283 how swap controller. Main change is that I'm
>>> now using the auxiliary bus for adding the GPIO device (done depending
>>> on FW properties).
>>>
>>> Similar to the LTC4282 device, we're clearing some fault logs in the
>>> reset_history attributes.
>>>
>>
>> I ran the patch series through an AI review. Results are below.
>> Please take a look.
>>
>> Thanks,
>> Guenter
>>
>> ---
>> # Deep Dive Regression Analysis Log
>> Date: 2026-01-27
>>
>> ## Commit 5998c620fbd8: gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller
>>
>> **Context**:
>> - Adds a new GPIO driver `drivers/gpio/gpio-ltc4283.c`.
>> - Depends on `drivers/hwmon/ltc4283.c` for regmap and MFD instantiation.
>>
>> **Findings**:
>> 1.  **Typo/Naming Issue**:
>>       - File `drivers/gpio/gpio-ltc4283.c` uses `LTC42823_ADIO_CONFIG` definition.
>>       - `LTC42823` appears to be a typo for `LTC4283`.
>>       - `drivers/gpio/gpio-ltc4283.c:26`: `#define LTC42823_ADIO_CONFIG 0x12`
>>
>> 2.  **Logic Verification**:
>>       - GPIO direction and value setting logic appears consistent with bitmasks provided, assuming
>> register `0x12` and `0x11` layout is correct as inferred.
>>
>> 3.  **Regressions**:
>>       - No critical functional regressions found in this commit alone.
>>       - Code quality: Typo in macro name.
>>
>> ## Commit 82433332ce16: hwmon: ltc4283: Add support for the LTC4283 Swap Controller
>>
>> **Context**:
>> - Adds core HWMON driver `drivers/hwmon/ltc4283.c`.
>> - Handles I2C communication, regmap initialization, and MFD child creation.
>>
>> **Findings**:
>> 1.  **Critical Regression: DebugFS Use-After-Free**:
>>       - `ltc4283_probe` calls `ltc4283_debugfs_init`.
>>       - `ltc4283_debugfs_init` calls `debugfs_create_file_unsafe` creating files associated with
>> `st`.
>>       - `st` is allocated with `devm_kzalloc`.
>>       - **Issue**: There is no explicit cleanup of debugfs entries (e.g.,
>> `debugfs_remove_recursive`) and no `devm_add_action` to handle it.
>>       - **Consequence**: When the driver is unbound/unloaded, `st` is freed by devm. The debugfs
>> entries remain. Accessing them triggers a Use-After-Free on `st`.
>>       - **Fix Required**: Use `devm_add_action_or_reset` to remove debugfs directory/entries on
>> driver detach.
> 
> So actually a nice deduction from the agent but not accurate given that all the entries should be
> removed in [1]. If you want it to be explicit, I can add the action but given that the dentry is
> given by i2c, I would argue it's fair to assume i2c will take care of the removal. Thoughts?
> 

Good point. You are correct. I'll need to tell the agent about this.

> I'm also planning to pick this up again but was caught by something else. So hopefully next week.
> 
> On another topic, I also (you questioned it in another thread) looked around and I do have a ltc4282
> board with me. Given that I just need to power up the digital parts to access the i2c bus, it should
> be pretty straight to get a register dump. So if you're still interested on that, I should be able
> to do it.
> 
Yes, that would be great.

Thanks!

Guenter

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

On Wed, Jan 28, 2026 at 02:04:35AM -0800, Guenter Roeck wrote:
> On 1/28/26 01:44, Nuno Sá wrote:
> > Hi Guenter,
> > 
> > On Tue, 2026-01-27 at 09:39 -0800, Guenter Roeck wrote:
> > > Hi Nuno,
> > > 
> > > On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> > > > This is v3 for the LTC4283 how swap controller. Main change is that I'm
> > > > now using the auxiliary bus for adding the GPIO device (done depending
> > > > on FW properties).
> > > > 
> > > > Similar to the LTC4282 device, we're clearing some fault logs in the
> > > > reset_history attributes.
> > > > 
> > > 
> > > I ran the patch series through an AI review. Results are below.
> > > Please take a look.
> > > 

Another run through AI below. Please let me know if there are further inaccuracies.

Thanks,
Guenter

---
commit 82433332ce165903d56fae327ced975aeef30475
Author:     Nuno Sá <nuno.sa@analog.com>

hwmon: ltc4283: Add support for the LTC4283 Swap Controller

Adds support for the LTC4283 Hot Swap Controller I2C interface.

> diff --git a/drivers/hwmon/ltc4283.c b/drivers/hwmon/ltc4283.c
> new file mode 100644
> index 000000000000..402b53f81548
> --- /dev/null
> +++ b/drivers/hwmon/ltc4283.c

[ ... ]

> +static int ltc4283_read_power_word(const struct ltc4283_hwmon *st,
> +				   u32 reg, long *val)
> +{
> +	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> +	unsigned int __raw;
> +	int ret;
> +
> +	ret = regmap_read(st->map_word, reg, &__raw);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Power is given by:
> +	 *     P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense)
> +	 */
> +	*val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense);

Does this overflow *val on 32-bit systems if the calculated power exceeds
2000 Watts (approx 2^31 microWatts)?  The intermediate calculation is
u64, but the result is assigned to a signed long.

[ ... ]

> +static bool ltc4283_word_reg(struct device *dev, unsigned int reg)
> +{
> +	switch (reg) {
> +	case LTC4283_SENSE ... LTC4283_ADIO34_MAX:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}

LTC4283_SENSE is 0x41 and LTC4283_ADIO34_MAX is 0x40.  Does this invalid
range (start > end) effectively disable access to the word registers
via st->map_word?

> +static const struct regmap_config ltc4283_word_regmap_config = {
> +	.name = "ltc4283-16",
> +	.reg_bits = 8,
> +	.val_bits = 16,
> +	.max_register = LTC4283_ADIO34_MAX,
> +	.val_format_endian = REGMAP_ENDIAN_BIG,
> +	.writeable_reg = ltc4283_word_reg,
> +	.readable_reg = ltc4283_word_reg,
> +};

Does max_register = 0x40 prevent access to the sensor value registers
(LTC4283_SENSE at 0x41 and above) which are intended to be read as
words?

commit 5998c620fbd8915340a4b92635c9489a91fae567
Author:     Nuno Sá <nuno.sa@analog.com>

gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller

Adds GPIO support for the LTC4283.

> diff --git a/drivers/gpio/gpio-ltc4283.c b/drivers/gpio/gpio-ltc4283.c
> new file mode 100644
> index 000000000000..fa0c106d4fac
> --- /dev/null
> +++ b/drivers/gpio/gpio-ltc4283.c

[ ... ]

> +#define LTC4283_PINS_MAX			8
> +#define LTC4283_PGIOX_START_NR			4
> +#define LTC4283_INPUT_STATUS			0x02
> +#define LTC4283_PGIO_CONFIG			0x10
> +#define   LTC4283_PGIO_CFG_MASK(pin) 
> +	GENMASK(((pin) - LTC4283_PGIOX_START_NR) * 2 + 1, (((pin) - LTC4283_PGIOX_START_NR) * 2))
> +#define LTC4283_PGIO_CONFIG_2			0x11
> +
> +#define LTC42823_ADIO_CONFIG			0x12

This isn't a bug, but should this be LTC4283_ADIO_CONFIG instead of
LTC42823?

> +/* starts at bit 4 */
> +#define   LTC4283_ADIOX_CONFIG_MASK(pin)	BIT((pin) + 4)
> +#define LTC4283_PGIO_DIR_IN			3
> +#define LTC4283_PGIO_DIR_OUT			2

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Nuno Sá]

On Wed, 2026-01-28 at 08:55 -0800, Guenter Roeck wrote:
> On Wed, Jan 28, 2026 at 02:04:35AM -0800, Guenter Roeck wrote:
> > On 1/28/26 01:44, Nuno Sá wrote:
> > > Hi Guenter,
> > > 
> > > On Tue, 2026-01-27 at 09:39 -0800, Guenter Roeck wrote:
> > > > Hi Nuno,
> > > > 
> > > > On 12/23/25 04:21, Nuno Sá via B4 Relay wrote:
> > > > > This is v3 for the LTC4283 how swap controller. Main change is that I'm
> > > > > now using the auxiliary bus for adding the GPIO device (done depending
> > > > > on FW properties).
> > > > > 
> > > > > Similar to the LTC4282 device, we're clearing some fault logs in the
> > > > > reset_history attributes.
> > > > > 
> > > > 
> > > > I ran the patch series through an AI review. Results are below.
> > > > Please take a look.
> > > > 
> 
> Another run through AI below. Please let me know if there are further inaccuracies.
> 
> Thanks,
> Guenter
> 
> ---
> commit 82433332ce165903d56fae327ced975aeef30475
> Author:     Nuno Sá <nuno.sa@analog.com>
> 
> hwmon: ltc4283: Add support for the LTC4283 Swap Controller
> 
> Adds support for the LTC4283 Hot Swap Controller I2C interface.
> 
> > diff --git a/drivers/hwmon/ltc4283.c b/drivers/hwmon/ltc4283.c
> > new file mode 100644
> > index 000000000000..402b53f81548
> > --- /dev/null
> > +++ b/drivers/hwmon/ltc4283.c
> 
> [ ... ]
> 
> > +static int ltc4283_read_power_word(const struct ltc4283_hwmon *st,
> > +				   u32 reg, long *val)
> > +{
> > +	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> > +	unsigned int __raw;
> > +	int ret;
> > +
> > +	ret = regmap_read(st->map_word, reg, &__raw);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/*
> > +	 * Power is given by:
> > +	 *     P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense)
> > +	 */
> > +	*val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense);
> 
> Does this overflow *val on 32-bit systems if the calculated power exceeds
> 2000 Watts (approx 2^31 microWatts)?  The intermediate calculation is
> u64, but the result is assigned to a signed long.
> 

I'll have to double check this one but IIRC 2000W is not a realistic value for
these applications. One thing that could overflow is power_max given that the default
register value is 0xff but we do write the proper max value depending on
rsense (I actually need to check how will this behave in case we use a default
rsense value - ie with no DT property).

> [ ... ]
> 
> > +static bool ltc4283_word_reg(struct device *dev, unsigned int reg)
> > +{
> > +	switch (reg) {
> > +	case LTC4283_SENSE ... LTC4283_ADIO34_MAX:
> > +		return true;
> > +	default:
> > +		return false;
> > +	}
> > +}
> 
> LTC4283_SENSE is 0x41 and LTC4283_ADIO34_MAX is 0x40.  Does this invalid
> range (start > end) effectively disable access to the word registers
> via st->map_word?

The above is odd ad I'm pretty sure I ran sensors on this but could be some late edit
mistake. Anyways irrelevant for the next version as you prefer the custom bus regmap
approach.

> 
> > +static const struct regmap_config ltc4283_word_regmap_config = {
> > +	.name = "ltc4283-16",
> > +	.reg_bits = 8,
> > +	.val_bits = 16,
> > +	.max_register = LTC4283_ADIO34_MAX,
> > +	.val_format_endian = REGMAP_ENDIAN_BIG,
> > +	.writeable_reg = ltc4283_word_reg,
> > +	.readable_reg = ltc4283_word_reg,
> > +};
> 
> Does max_register = 0x40 prevent access to the sensor value registers
> (LTC4283_SENSE at 0x41 and above) which are intended to be read as
> words?

ditto

> 
> commit 5998c620fbd8915340a4b92635c9489a91fae567
> Author:     Nuno Sá <nuno.sa@analog.com>
> 
> gpio: gpio-ltc4283: Add support for the LTC4283 Swap Controller
> 
> Adds GPIO support for the LTC4283.
> 
> > diff --git a/drivers/gpio/gpio-ltc4283.c b/drivers/gpio/gpio-ltc4283.c
> > new file mode 100644
> > index 000000000000..fa0c106d4fac
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-ltc4283.c
> 
> [ ... ]
> 
> > +#define LTC4283_PINS_MAX			8
> > +#define LTC4283_PGIOX_START_NR			4
> > +#define LTC4283_INPUT_STATUS			0x02
> > +#define LTC4283_PGIO_CONFIG			0x10
> > +#define   LTC4283_PGIO_CFG_MASK(pin) 
> > +	GENMASK(((pin) - LTC4283_PGIOX_START_NR) * 2 + 1, (((pin) - LTC4283_PGIOX_START_NR) *
> > 2))
> > +#define LTC4283_PGIO_CONFIG_2			0x11
> > +
> > +#define LTC42823_ADIO_CONFIG			0x12
> 
> This isn't a bug, but should this be LTC4283_ADIO_CONFIG instead of
> LTC42823?

Indeed!

- Nuno Sá
		2

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Guenter Roeck]

On Wed, Jan 28, 2026 at 06:07:24PM +0000, Nuno Sá wrote:
> > [ ... ]
> > 
> > > +static int ltc4283_read_power_word(const struct ltc4283_hwmon *st,
> > > +				   u32 reg, long *val)
> > > +{
> > > +	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> > > +	unsigned int __raw;
> > > +	int ret;
> > > +
> > > +	ret = regmap_read(st->map_word, reg, &__raw);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	/*
> > > +	 * Power is given by:
> > > +	 *     P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense)
> > > +	 */
> > > +	*val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense);
> > 
> > Does this overflow *val on 32-bit systems if the calculated power exceeds
> > 2000 Watts (approx 2^31 microWatts)?  The intermediate calculation is
> > u64, but the result is assigned to a signed long.
> > 
> 
> I'll have to double check this one but IIRC 2000W is not a realistic value for
> these applications. One thing that could overflow is power_max given that the default
> register value is 0xff but we do write the proper max value depending on
> rsense (I actually need to check how will this behave in case we use a default
> rsense value - ie with no DT property).
> 

I have been wondering if I should introduce a hwmon_power64 sensor type, similar to
hwmon_energy64. WDYT ?

Thanks,
Guenter

Re: [PATCH v5 0/3] hwmon: Add support for the LTC4283 Hot Swap Controller

[Nuno Sá]

On Wed, 2026-01-28 at 10:22 -0800, Guenter Roeck wrote:
> On Wed, Jan 28, 2026 at 06:07:24PM +0000, Nuno Sá wrote:
> > > [ ... ]
> > > 
> > > > +static int ltc4283_read_power_word(const struct ltc4283_hwmon *st,
> > > > +				   u32 reg, long *val)
> > > > +{
> > > > +	u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI;
> > > > +	unsigned int __raw;
> > > > +	int ret;
> > > > +
> > > > +	ret = regmap_read(st->map_word, reg, &__raw);
> > > > +	if (ret)
> > > > +		return ret;
> > > > +
> > > > +	/*
> > > > +	 * Power is given by:
> > > > +	 *     P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense)
> > > > +	 */
> > > > +	*val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense);
> > > 
> > > Does this overflow *val on 32-bit systems if the calculated power exceeds
> > > 2000 Watts (approx 2^31 microWatts)?  The intermediate calculation is
> > > u64, but the result is assigned to a signed long.
> > > 
> > 
> > I'll have to double check this one but IIRC 2000W is not a realistic value for
> > these applications. One thing that could overflow is power_max given that the default
> > register value is 0xff but we do write the proper max value depending on
> > rsense (I actually need to check how will this behave in case we use a default
> > rsense value - ie with no DT property).
> > 
> 
> I have been wondering if I should introduce a hwmon_power64 sensor type, similar to
> hwmon_energy64. WDYT ?
> 

No strong opinion. As I said, not sure if it's needed here but OTOH given that power is
microWatts I guess it's a matter of time. Anyways, if you do it, I might as well just play safe
and use it in here (and ltc4282 should also be converted - likely).

- Nuno Sá