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Mon, 11 Sep 2023 15:07:24 GMT Received: from [10.216.14.127] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Mon, 11 Sep 2023 08:07:09 -0700 Message-ID: <9da888dc-401a-4cbb-b616-b4654fa79e35@quicinc.com> Date: Mon, 11 Sep 2023 20:37:03 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [REBASE PATCH v5 15/17] firmware: scm: Modify only the download bits in TCSR register Content-Language: en-US To: Mukesh Ojha , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , "Poovendhan Selvaraj" References: <1694429639-21484-1-git-send-email-quic_mojha@quicinc.com> <1694429639-21484-16-git-send-email-quic_mojha@quicinc.com> From: Kathiravan Thirumoorthy In-Reply-To: <1694429639-21484-16-git-send-email-quic_mojha@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZDO2ULWUeou-4qYw_-dQxukWf0tQGiKd X-Proofpoint-GUID: ZDO2ULWUeou-4qYw_-dQxukWf0tQGiKd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-11_10,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 suspectscore=0 clxscore=1015 adultscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309110138 Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On 9/11/2023 4:23 PM, Mukesh Ojha wrote: > Crashdump collection is based on the DLOAD bit of TCSR register. > To retain other bits, we read the register and modify only the > DLOAD bit as the other bits have their own significance. > > Co-developed-by: Poovendhan Selvaraj > Signed-off-by: Poovendhan Selvaraj > Signed-off-by: Mukesh Ojha > Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 > --- > drivers/firmware/qcom_scm.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c > index 321133f0950d..5cacae63ee2a 100644 > --- a/drivers/firmware/qcom_scm.c > +++ b/drivers/firmware/qcom_scm.c > @@ -5,6 +5,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -26,6 +28,14 @@ > static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); > module_param(download_mode, bool, 0); > > +#define SCM_HAS_CORE_CLK BIT(0) > +#define SCM_HAS_IFACE_CLK BIT(1) > +#define SCM_HAS_BUS_CLK BIT(2) Is this intentional to add these macros back again? > + > +#define QCOM_DLOAD_MASK GENMASK(5, 4) > +#define QCOM_DLOAD_FULLDUMP 0x1 > +#define QCOM_DLOAD_NODUMP 0x0 > + > struct qcom_scm { > struct device *dev; > struct clk *core_clk; > @@ -440,6 +450,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) > > static void qcom_scm_set_download_mode(bool enable) > { > + u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP; > bool avail; > int ret = 0; > > @@ -449,8 +460,9 @@ static void qcom_scm_set_download_mode(bool enable) > if (avail) { > ret = __qcom_scm_set_dload_mode(__scm->dev, enable); > } else if (__scm->dload_mode_addr) { > - ret = qcom_scm_io_writel(__scm->dload_mode_addr, > - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); > + ret = qcom_scm_io_update_field(__scm->dload_mode_addr, > + QCOM_DLOAD_MASK, > + FIELD_PREP(QCOM_DLOAD_MASK, val)); > } else { > dev_err(__scm->dev, > "No available mechanism for setting download mode\n");