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[209.85.219.170]) by smtp.gmail.com with ESMTPSA id 00721157ae682-70a3d9cb5ccsm29779187b3.90.2025.05.14.09.26.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 May 2025 09:26:49 -0700 (PDT) Received: by mail-yb1-f170.google.com with SMTP id 3f1490d57ef6-e78f528aa8eso6069068276.3; Wed, 14 May 2025 09:26:49 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCUQL6ZUqYR60/mjV7HZhQEUUW3dKH/vXljeyx4HVQPs53n/4gdMFXJA60weEhzFTn9PbJPN0f/vY2QqEHr3@vger.kernel.org, AJvYcCUkiGgBr2jDg+RYBsWsC6RF+sbXYhchzxbvXkmUid1KIu74NSQ52V5i1zj7LZBhXSQfJuuLC9kFnYIj@vger.kernel.org, AJvYcCUrtu+y4sofV1DOlWAtNJKGYdJdeQ3kPSMCaDUI7en2vDddYaeBCRz6BMixfN+3/ZPvzdwY0o3SchsGZq0=@vger.kernel.org, AJvYcCVcOXqOIpGd59hPHSY2ywtDrnJ3+QTcI6Kis0KdjT/oMPW7lFkqx5un/W9UnT9spgVJRek7n+8cQRbW@vger.kernel.org X-Received: by 2002:a05:6902:1202:b0:e6d:f160:bbdf with SMTP id 3f1490d57ef6-e7b3d59ae2fmr4832866276.36.1747240009056; Wed, 14 May 2025 09:26:49 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250225-6-10-rocket-v2-0-d4dbcfafc141@tomeuvizoso.net> <20250225-6-10-rocket-v2-1-d4dbcfafc141@tomeuvizoso.net> <20250225160248.GA2563229-robh@kernel.org> In-Reply-To: <20250225160248.GA2563229-robh@kernel.org> From: Tomeu Vizoso Date: Wed, 14 May 2025 18:26:38 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AX0GCFvDEBwxCoW2ZGLJEEIKb_2H5q_lCEI2NWi7ZFVAMNUkSoshPa20AanOMV0 Message-ID: Subject: Re: [PATCH v2 1/7] dt-bindings: npu: rockchip,rknn: Add bindings To: Rob Herring Cc: Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Oded Gabbay , Jonathan Corbet , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= , Sebastian Reichel , Jeffrey Hugo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Rob, On Tue, Feb 25, 2025 at 5:02=E2=80=AFPM Rob Herring wrote= : > > On Tue, Feb 25, 2025 at 08:55:47AM +0100, Tomeu Vizoso wrote: > > Add the bindings for the Neural Processing Unit IP from Rockchip. > > > > v2: > > - Adapt to new node structure (one node per core, each with its own > > IOMMU) > > - Several misc. fixes from Sebastian Reichel > > > > Signed-off-by: Tomeu Vizoso > > Signed-off-by: Sebastian Reichel > > --- > > .../bindings/npu/rockchip,rknn-core.yaml | 152 +++++++++++++= ++++++++ > > 1 file changed, 152 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn-core.y= aml b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml > > new file mode 100644 > > index 0000000000000000000000000000000000000000..e8d0afe4a7d1c4f166cf13a= 9f4aa7c1901362a3f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml > > @@ -0,0 +1,152 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/npu/rockchip,rknn-core.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Neural Processing Unit IP from Rockchip > > + > > +maintainers: > > + - Tomeu Vizoso > > + > > +description: > > + Rockchip IP for accelerating inference of neural networks, based on = NVIDIA's > > + open source NVDLA IP. > > + > > +properties: > > + $nodename: > > + pattern: '^npu-core@[a-f0-9]+$' > > + > > + compatible: > > + oneOf: > > + - items: > > + - enum: > > + - rockchip,rk3588-rknn-core-top > > + - const: rockchip,rknn-core-top > > Drop the fallbacks unless you have some evidence that the IP is the > same across a lot of SoCs. If you don't, then > rockchip,rk3588-rknn-core-top can be the fallback whenever there are > more compatible SoCs. > > Or if there's version/feature registers that otherwise make it > discoverable, then a common compatible is fine. > > > + - items: > > + - enum: > > + - rockchip,rk3588-rknn-core > > + - const: rockchip,rknn-core > > I don't understand the difference between core and core-top. That needs > to be explained in the top-level description. > > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 2 > > + maxItems: 4 > > + > > + clock-names: > > + items: > > + - const: aclk > > + - const: hclk > > + - const: npu > > + - const: pclk > > + minItems: 2 > > + > > + interrupts: > > + maxItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > + npu-supply: true > > + > > + power-domains: > > + maxItems: 1 > > + > > + resets: > > + maxItems: 2 > > + > > + reset-names: > > + items: > > + - const: srst_a > > + - const: srst_h > > + > > + sram-supply: true > > Group supply properties together > > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - iommus > > + - npu-supply > > + - power-domains > > + - resets > > + - reset-names > > + - sram-supply > > + > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - rockchip,rknn-core-top > > + then: > > + properties: > > + clocks: > > + minItems: 4 > > + > > + clock-names: > > + minItems: 4 > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - rockchip,rknn-core > > + then: > > + properties: > > + clocks: > > + maxItems: 2 > > + clock-names: > > + maxItems: 2 > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + #include > > + #include > > + #include > > + #include > > + > > + bus { > > + #address-cells =3D <2>; > > + #size-cells =3D <2>; > > + > > + rknn_core_top: npu-core@fdab0000 { > > npu@... Can you extend on why you would prefer to have npu@? As each node corresponds to a core inside the NPU, I went with npu-core@. Thanks, Tomeu > > + compatible =3D "rockchip,rk3588-rknn-core-top", "rockchip,rknn= -core-top"; > > + reg =3D <0x0 0xfdab0000 0x0 0x9000>; > > + assigned-clocks =3D <&scmi_clk SCMI_CLK_NPU>; > > + assigned-clock-rates =3D <200000000>; > > + clocks =3D <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, > > + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; > > + clock-names =3D "aclk", "hclk", "npu", "pclk"; > > + interrupts =3D ; > > + iommus =3D <&rknn_mmu_top>; > > + npu-supply =3D <&vdd_npu_s0>; > > + power-domains =3D <&power RK3588_PD_NPUTOP>; > > + resets =3D <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; > > + reset-names =3D "srst_a", "srst_h"; > > + sram-supply =3D <&vdd_npu_mem_s0>; > > + }; > > + > > + rknn_core_1: npu-core@fdac0000 { > > + compatible =3D "rockchip,rk3588-rknn-core", "rockchip,rknn-cor= e"; > > + reg =3D <0x0 0xfdac0000 0x0 0x9000>; > > + clocks =3D <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; > > + clock-names =3D "aclk", "hclk"; > > + interrupts =3D ; > > + iommus =3D <&rknn_mmu_1>; > > + npu-supply =3D <&vdd_npu_s0>; > > + power-domains =3D <&power RK3588_PD_NPU1>; > > + resets =3D <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>; > > + reset-names =3D "srst_a", "srst_h"; > > + sram-supply =3D <&vdd_npu_mem_s0>; > > + }; > > + }; > > +... > > > > -- > > 2.48.1 > >