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AJvYcCUBXm7Is8Cm2A1/pFhIGfYTvuWMVelcS+tA87/ou6shsHeSf9R8L5Ci7EpBIj16ckrdtot+ePigGv4=@vger.kernel.org X-Gm-Message-State: AOJu0YzpOFNdFWWU9TiAdhm+4KZAlmjY4g+4bAi0tjcj2U49eezhP153 9RtyUFT4YFKx9o+/FXiqEGL9uVjeoUIYDGuu4314YidDFiXTkrVvrcRVELfIyxA6mr3jKclz+pc 0JaqWuYfAmf1T0eX8pKC4HOf4Xxjr0jJj5gcjkoiTIQ== X-Gm-Gg: ASbGnctnp1+UxoEKlPf5h+mpzt+z3TjURya4UCCi57Fye50x7uYzpwk9jlzMvGNL6sv icWXg69f66mZKE+o4UCq9MjvY0uT2SA+ftUhcnpw8xOUrFDz6lfsCF8ticcff7xFtvnIPHuxh7n d2LIFM3yfPREnEVDirrkTxsTcegFDXxZPoUJrtbsd3xcJ1 X-Google-Smtp-Source: AGHT+IG2iBZqXBZpblYqqV1CfizkbcXBVYuUqCYGloOAj0H2lvAJwOXwnS5XNnZkQ46BncD7OmhOhE+Hobvx1RtA1UQ= X-Received: by 2002:a05:6e02:1807:b0:3dd:8663:d182 with SMTP id e9e14a558f8ab-3ddf42c5b4dmr72461125ab.13.1749734805782; Thu, 12 Jun 2025 06:26:45 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-15-cleger@rivosinc.com> In-Reply-To: <20250523101932.1594077-15-cleger@rivosinc.com> From: Anup Patel Date: Thu, 12 Jun 2025 18:56:33 +0530 X-Gm-Features: AX0GCFtHBaD1dkadFboJHCaCDko1UoltJB37LuW30sdZ0j57mmaziXXBSUbao7Y Message-ID: Subject: Re: [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG To: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Paul Walmsley , Palmer Dabbelt , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta , Charlie Jenkins , Atish Patra Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, May 23, 2025 at 3:53=E2=80=AFPM Cl=C3=A9ment L=C3=A9ger wrote: > > SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate > misaligned load/store exceptions. Save and restore it during CPU > load/put. > > Signed-off-by: Cl=C3=A9ment L=C3=A9ger > Reviewed-by: Deepak Gupta > Reviewed-by: Andrew Jones > Reviewed-by: Atish Patra Queued this patch for Linux-6.17 Thanks, Anup > --- > arch/riscv/kvm/vcpu_sbi_fwft.c | 41 ++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwf= t.c > index b0f66c7bf010..6770c043bbcb 100644 > --- a/arch/riscv/kvm/vcpu_sbi_fwft.c > +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c > @@ -14,6 +14,8 @@ > #include > #include > > +#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISA= LIGNED)) > + > struct kvm_sbi_fwft_feature { > /** > * @id: Feature ID > @@ -68,7 +70,46 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_= feature_t feature) > return false; > } > > +static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu= *vcpu) > +{ > + return misaligned_traps_can_delegate(); > +} > + > +static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu= , > + struct kvm_sbi_fwft_config *conf, > + unsigned long value) > +{ > + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; > + > + if (value =3D=3D 1) { > + cfg->hedeleg |=3D MIS_DELEG; > + csr_set(CSR_HEDELEG, MIS_DELEG); > + } else if (value =3D=3D 0) { > + cfg->hedeleg &=3D ~MIS_DELEG; > + csr_clear(CSR_HEDELEG, MIS_DELEG); > + } else { > + return SBI_ERR_INVALID_PARAM; > + } > + > + return SBI_SUCCESS; > +} > + > +static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu= , > + struct kvm_sbi_fwft_config *conf, > + unsigned long *value) > +{ > + *value =3D (csr_read(CSR_HEDELEG) & MIS_DELEG) =3D=3D MIS_DELEG; > + > + return SBI_SUCCESS; > +} > + > static const struct kvm_sbi_fwft_feature features[] =3D { > + { > + .id =3D SBI_FWFT_MISALIGNED_EXC_DELEG, > + .supported =3D kvm_sbi_fwft_misaligned_delegation_support= ed, > + .set =3D kvm_sbi_fwft_set_misaligned_delegation, > + .get =3D kvm_sbi_fwft_get_misaligned_delegation, > + }, > }; > > static struct kvm_sbi_fwft_config * > -- > 2.49.0 >