From: Huacai Chen <chenhuacai@gmail.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Huacai Chen <chenhuacai@loongson.cn>,
Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>, Jonathan Corbet <corbet@lwn.net>,
Linus Torvalds <torvalds@linux-foundation.org>,
linux-arch <linux-arch@vger.kernel.org>,
"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Xuefeng Li <lixuefeng@loongson.cn>,
Yanteng Si <siyanteng@loongson.cn>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: Re: [PATCH V4 07/22] LoongArch: Add atomic/locking headers
Date: Sat, 2 Oct 2021 19:47:58 +0800 [thread overview]
Message-ID: <CAAhV-H7MNU7oYMH44hrjFGKQvmDrgbBKAy2e8dfrMWq=bgxBQA@mail.gmail.com> (raw)
In-Reply-To: <YVbogd2gihouyWJd@hirez.programming.kicks-ass.net>
Hi, Peter,
On Fri, Oct 1, 2021 at 6:54 PM Peter Zijlstra <peterz@infradead.org> wrote:
>
> On Mon, Sep 27, 2021 at 02:42:44PM +0800, Huacai Chen wrote:
> > diff --git a/arch/loongarch/include/asm/bitops.h b/arch/loongarch/include/asm/bitops.h
> > new file mode 100644
> > index 000000000000..8b05d9683571
> > --- /dev/null
> > +++ b/arch/loongarch/include/asm/bitops.h
> > @@ -0,0 +1,220 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2020-2021 Loongson Technology Corporation Limited
> > + */
> > +#ifndef _ASM_BITOPS_H
> > +#define _ASM_BITOPS_H
> > +
> > +#ifndef _LINUX_BITOPS_H
> > +#error only <linux/bitops.h> can be included directly
> > +#endif
> > +
> > +#include <linux/compiler.h>
> > +#include <linux/types.h>
> > +#include <asm/barrier.h>
> > +#include <asm/byteorder.h>
> > +#include <asm/compiler.h>
> > +#include <asm/cpu-features.h>
> > +
> > +#if _LOONGARCH_SZLONG == 32
> > +#define __LL "ll.w "
> > +#define __SC "sc.w "
> > +#define __AMADD "amadd.w "
> > +#define __AMAND_SYNC "amand_db.w "
> > +#define __AMOR_SYNC "amor_db.w "
> > +#define __AMXOR_SYNC "amxor_db.w "
> > +#elif _LOONGARCH_SZLONG == 64
> > +#define __LL "ll.d "
> > +#define __SC "sc.d "
> > +#define __AMADD "amadd.d "
> > +#define __AMAND_SYNC "amand_db.d "
> > +#define __AMOR_SYNC "amor_db.d "
> > +#define __AMXOR_SYNC "amxor_db.d "
> > +#endif
> > +
> > +/*
> > + * set_bit - Atomically set a bit in memory
> > + * @nr: the bit to set
> > + * @addr: the address to start counting from
> > + */
> > +static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMOR_SYNC "$zero, %1, %0 \n"
> > + : "+ZB" (*m)
> > + : "r" (1UL << bit)
> > + : "memory");
> > +}
> > +
> > +/*
> > + * clear_bit - Clears a bit in memory
> > + * @nr: Bit to clear
> > + * @addr: Address to start counting from
> > + */
> > +static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMAND_SYNC "$zero, %1, %0 \n"
> > + : "+ZB" (*m)
> > + : "r" (~(1UL << bit))
> > + : "memory");
> > +}
> > +
> > +/*
> > + * clear_bit_unlock - Clears a bit in memory
> > + * @nr: Bit to clear
> > + * @addr: Address to start counting from
> > + */
> > +static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
> > +{
> > + clear_bit(nr, addr);
> > +}
> > +
> > +/*
> > + * change_bit - Toggle a bit in memory
> > + * @nr: Bit to change
> > + * @addr: Address to start counting from
> > + */
> > +static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMXOR_SYNC "$zero, %1, %0 \n"
> > + : "+ZB" (*m)
> > + : "r" (1UL << bit)
> > + : "memory");
> > +}
> > +
> > +/*
> > + * test_and_set_bit - Set a bit and return its old value
> > + * @nr: Bit to set
> > + * @addr: Address to count from
> > + */
> > +static inline int test_and_set_bit(unsigned long nr,
> > + volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + unsigned long res;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMOR_SYNC "%1, %2, %0 \n"
> > + : "+ZB" (*m), "=&r" (res)
> > + : "r" (1UL << bit)
> > + : "memory");
> > +
> > + res = res & (1UL << bit);
> > +
> > + return res != 0;
> > +}
> > +
> > +/*
> > + * test_and_set_bit_lock - Set a bit and return its old value
> > + * @nr: Bit to set
> > + * @addr: Address to count from
> > + */
> > +static inline int test_and_set_bit_lock(unsigned long nr,
> > + volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + unsigned long res;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMOR_SYNC "%1, %2, %0 \n"
> > + : "+ZB" (*m), "=&r" (res)
> > + : "r" (1UL << bit)
> > + : "memory");
> > +
> > + res = res & (1UL << bit);
> > +
> > + return res != 0;
> > +}
> > +/*
> > + * test_and_clear_bit - Clear a bit and return its old value
> > + * @nr: Bit to clear
> > + * @addr: Address to count from
> > + */
> > +static inline int test_and_clear_bit(unsigned long nr,
> > + volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + unsigned long res, temp;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMAND_SYNC "%1, %2, %0 \n"
> > + : "+ZB" (*m), "=&r" (temp)
> > + : "r" (~(1UL << bit))
> > + : "memory");
> > +
> > + res = temp & (1UL << bit);
> > +
> > + return res != 0;
> > +}
> > +
> > +/*
> > + * test_and_change_bit - Change a bit and return its old value
> > + * @nr: Bit to change
> > + * @addr: Address to count from
> > + */
> > +static inline int test_and_change_bit(unsigned long nr,
> > + volatile unsigned long *addr)
> > +{
> > + int bit = nr % BITS_PER_LONG;
> > + unsigned long res;
> > + volatile unsigned long *m = &addr[BIT_WORD(nr)];
> > +
> > + __asm__ __volatile__(
> > + " " __AMXOR_SYNC "%1, %2, %0 \n"
> > + : "+ZB" (*m), "=&r" (res)
> > + : "r" (1UL << bit)
> > + : "memory");
> > +
> > + res = res & (1UL << bit);
> > +
> > + return res != 0;
> > +}
>
> Why is asm-generic/bitops/atomic.h not working for you?
It seems that __clear_bit_unlock() needs an additional mb() after the
generic version, all other functions are the same as the generic
version.
Huacai
>
next prev parent reply other threads:[~2021-10-02 11:48 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-27 6:42 [PATCH V4 00/22] arch: Add basic LoongArch support Huacai Chen
2021-09-27 6:42 ` [PATCH V4 01/22] Documentation: LoongArch: Add basic documentations Huacai Chen
2021-09-27 6:42 ` [PATCH V4 02/22] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen
2021-09-27 6:42 ` [PATCH V4 03/22] LoongArch: Add elf-related definitions Huacai Chen
2021-09-27 6:42 ` [PATCH V4 04/22] LoongArch: Add writecombine support for drm Huacai Chen
2021-09-27 6:42 ` [PATCH V4 05/22] LoongArch: Add build infrastructure Huacai Chen
2021-09-27 6:42 ` [PATCH V4 06/22] LoongArch: Add CPU definition headers Huacai Chen
2021-09-30 15:30 ` Xi Ruoyao
2021-10-02 10:49 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 07/22] LoongArch: Add atomic/locking headers Huacai Chen
2021-10-01 10:52 ` Peter Zijlstra
2021-10-02 11:47 ` Huacai Chen [this message]
2021-10-01 11:04 ` Peter Zijlstra
2021-10-02 11:05 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 08/22] LoongArch: Add other common headers Huacai Chen
2021-09-27 6:42 ` [PATCH V4 09/22] LoongArch: Add boot and setup routines Huacai Chen
2021-09-27 6:52 ` Ard Biesheuvel
2021-09-29 3:24 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 10/22] LoongArch: Add exception/interrupt handling Huacai Chen
2021-09-27 6:42 ` [PATCH V4 11/22] LoongArch: Add process management Huacai Chen
2021-10-03 2:48 ` Al Viro
2021-10-03 9:10 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 12/22] LoongArch: Add memory management Huacai Chen
2021-09-27 6:42 ` [PATCH V4 13/22] LoongArch: Add system call support Huacai Chen
2021-09-27 6:42 ` [PATCH V4 14/22] LoongArch: Add signal handling support Huacai Chen
2021-10-03 2:29 ` Al Viro
2021-10-03 9:09 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 15/22] LoongArch: Add elf and module support Huacai Chen
2021-09-27 6:42 ` [PATCH V4 16/22] LoongArch: Add misc common routines Huacai Chen
2021-10-01 11:03 ` Peter Zijlstra
2021-10-02 10:56 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 17/22] LoongArch: Add some library functions Huacai Chen
2021-09-27 6:42 ` [PATCH V4 18/22] LoongArch: Add PCI controller support Huacai Chen
2021-09-27 6:42 ` [PATCH V4 19/22] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2021-09-30 15:43 ` Xi Ruoyao
2021-10-02 10:53 ` Huacai Chen
2021-10-02 12:13 ` Xi Ruoyao
2021-10-02 12:44 ` Huacai Chen
2021-09-27 6:42 ` [PATCH V4 20/22] LoongArch: Add multi-processor (SMP) support Huacai Chen
2021-09-27 6:42 ` [PATCH V4 21/22] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2021-09-27 6:42 ` [PATCH V4 22/22] LoongArch: Add Loongson-3 default config file Huacai Chen
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