From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on archive.lwn.net X-Spam-Level: X-Spam-Status: No, score=-5.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by archive.lwn.net (Postfix) with ESMTP id 72B0A7D57F for ; Mon, 24 Sep 2018 08:13:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726323AbeIXOOJ (ORCPT ); Mon, 24 Sep 2018 10:14:09 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:39488 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727159AbeIXOOJ (ORCPT ); Mon, 24 Sep 2018 10:14:09 -0400 Received: by mail-io1-f65.google.com with SMTP id l7-v6so16915437iok.6 for ; Mon, 24 Sep 2018 01:13:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=tuCpIlcdQTeV/K7rYvlgsPf7U0bVlHvEfKgiDfhDHvs=; b=VT32eHnsqo34eMWXwaJmjSagmgbjREwJEg3Oo655D0ogCmuCOq3AUW7CXZRJk4yHZW tyCdK19SnYanYL4kGt8YMw4cDC9bPfRxbCobVkISd9lPVRoNbBUZ3MDDVMbrC3Omjlh4 Ypy6dKJLFUtLRhgABiSr8N3xSUzzR6cs+xDM0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tuCpIlcdQTeV/K7rYvlgsPf7U0bVlHvEfKgiDfhDHvs=; b=d7Yj3TgldZXlYmC34baogglHJuQvsBQZm2R1S0Whd8gdEQaP0jKgnOXa0moN8wjmxn rhD4MDNowIhGJ877HA6a0tWT++RKX/suw9n0JzWTb8+/ZxP2FIpNMfobmKHuzq7TVLWq VSWFQ8wjMwJ8a3XkiT0Fx56uw4WNujrNvavtb5zeTHDniGudKrSdNh9gccbR/Es9TMg5 glFklE295PDxtNoQ6iVcMdu23gtbTefV9k0I3zsaMjOMLeElv6j+TmgyPuwkQeiUv6Iw IUl9q7Ya7pYXZEVyC+tbczAKztuUJOmuwpPPlFNHKbkPdTP4Ap3LSQnxNwHZULEHMugi nlOw== X-Gm-Message-State: ABuFfojyDx5GdKvpb/RIzij8odqruGK3+lA59y1kN1KH0L0yoeeFPtWc WlsVUZKW94dSY7C7n48maH26jYbc3YMA5oujrRjZdA== X-Google-Smtp-Source: ACcGV60jffR0gaxbH3Vbw/lU1LGhXZ36zx4v91f3ANt16Mo8JSUuDe3E9mRsPPUwcyg0oa6ijdsqsjzeDzVZ2kEPnaw= X-Received: by 2002:a6b:630a:: with SMTP id p10-v6mr7161376iog.175.1537776795785; Mon, 24 Sep 2018 01:13:15 -0700 (PDT) MIME-Version: 1.0 References: <2785169.v6aIfS3K2k@z50> <20180923235336.22148-1-jmkrzyszt@gmail.com> <20180923235336.22148-3-jmkrzyszt@gmail.com> In-Reply-To: <20180923235336.22148-3-jmkrzyszt@gmail.com> From: Linus Walleij Date: Mon, 24 Sep 2018 10:13:02 +0200 Message-ID: Subject: Re: [PATCH 2/2] gpiolib: Fix array members of same chip processed separately To: Janusz Krzysztofik Cc: Jonathan Corbet , Miguel Ojeda Sandonis , Peter Korsgaard , Peter Rosin , Ulf Hansson , Andrew Lunn , Florian Fainelli , "David S. Miller" , Dominik Brodowski , Greg KH , kishon@ti.com, Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Hartmut Knaack , Peter Meerwald , Jiri Slaby , Willy Tarreau , Geert Uytterhoeven , Sebastien Bourdelin , Lukas Wunner , Rojhalat Ibrahim , Russell King , ext Tony Lindgren , Yegor Yefremov , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , linux-doc@vger.kernel.org, linux-i2c@vger.kernel.org, linux-mmc , netdev , linux-iio@vger.kernel.org, devel@driverdev.osuosl.org, linux-serial@vger.kernel.org, "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Marek Szyprowski , Krzysztof Kozlowski , linux-samsung-soc Content-Type: text/plain; charset="UTF-8" Sender: linux-doc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Mon, Sep 24, 2018 at 1:52 AM Janusz Krzysztofik wrote: > New code introduced by commit bf9346f5d47b ("gpiolib: Identify arrays > matching GPIO hardware") forcibly tries to find an array member which > has its array index number equal to its hardware pin number and set > up an array info for possible fast bitmap processing of all arrray > pins belonging to that chip which also satisfy that numbering rule. > > Depending on array content, it may happen that consecutive array > members which belong to the same chip but don't have array indexes > equal to their pin hardware numbers will be split into groups, some of > them processed together via the fast bitmap path, and rest of them > separetely. However, applications may expect all those pins being > processed together with a single call to .set_multiple() chip callback, > like that was done before the change. > > Limit applicability of fast bitmap processing path to cases where all > pins of consecutive array members starting from 0 which belong to the > same chip have their hardware numbers equal to their corresponding > array indexes. That should still speed up processing of applications > using whole GPIO banks as I/O ports, while not breaking simultaneous > manipulation of consecutive pins of the same chip which don't follow > the equal numbering rule. > > Cc: Jonathan Corbet > Signed-off-by: Janusz Krzysztofik Patch applied! Yours, Linus Walleij