[PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

[PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

[Kirill A. Shutemov]

Both Intel and AMD CPUs support 5-level paging, which is expected to
become more widely adopted in the future.

Remove CONFIG_X86_5LEVEL.

In preparation to that remove CONFIG_DYNAMIC_MEMORY_LAYOUT and make
SPARSEMEM_VMEMMAP the only memory model.

v2:
 - Fix 32-bit build by wrapping p4d_set_huge() and p4d_clear_huge() in
   #if CONFIG_PGTABLE_LEVELS > 4;
 - Rebased onto current tip/master;

Kirill A. Shutemov (3):
  x86/64/mm: Always use dynamic memory layout
  x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model
  x86/64/mm: Make 5-level paging support unconditional

 Documentation/arch/x86/cpuinfo.rst            |  8 ++---
 .../arch/x86/x86_64/5level-paging.rst         |  9 ------
 arch/x86/Kconfig                              | 32 ++-----------------
 arch/x86/Kconfig.cpufeatures                  |  4 ---
 arch/x86/boot/compressed/pgtable_64.c         | 11 ++-----
 arch/x86/boot/header.S                        |  4 ---
 arch/x86/boot/startup/map_kernel.c            |  5 +--
 arch/x86/include/asm/page_64.h                |  2 --
 arch/x86/include/asm/page_64_types.h          | 11 -------
 arch/x86/include/asm/pgtable_64_types.h       | 24 --------------
 arch/x86/kernel/alternative.c                 |  2 +-
 arch/x86/kernel/head64.c                      |  4 ---
 arch/x86/kernel/head_64.S                     |  2 --
 arch/x86/mm/init.c                            |  4 ---
 arch/x86/mm/init_64.c                         |  9 +-----
 arch/x86/mm/pgtable.c                         |  2 +-
 drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
 scripts/gdb/linux/pgtable.py                  |  4 +--
 18 files changed, 13 insertions(+), 126 deletions(-)

-- 
2.47.2

[PATCHv2 1/3] x86/64/mm: Always use dynamic memory layout

[Kirill A. Shutemov]

Dynamic memory layout is used by KASLR and 5-level paging.

CONFIG_X86_5LEVEL is going to be removed, making 5-level paging support
unconditional which requires unconditional support of dynamic memory
layout.

Remove CONFIG_DYNAMIC_MEMORY_LAYOUT.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/Kconfig                        | 8 --------
 arch/x86/include/asm/page_64_types.h    | 4 ----
 arch/x86/include/asm/pgtable_64_types.h | 6 ------
 arch/x86/kernel/head64.c                | 2 --
 scripts/gdb/linux/pgtable.py            | 4 +---
 5 files changed, 1 insertion(+), 23 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 891a69b308cb..d3c2da3b2f0b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1467,7 +1467,6 @@ config X86_PAE
 config X86_5LEVEL
 	bool "Enable 5-level page tables support"
 	default y
-	select DYNAMIC_MEMORY_LAYOUT
 	select SPARSEMEM_VMEMMAP
 	depends on X86_64
 	help
@@ -2167,17 +2166,10 @@ config PHYSICAL_ALIGN
 
 	  Don't change this unless you know what you are doing.
 
-config DYNAMIC_MEMORY_LAYOUT
-	bool
-	help
-	  This option makes base addresses of vmalloc and vmemmap as well as
-	  __PAGE_OFFSET movable during boot.
-
 config RANDOMIZE_MEMORY
 	bool "Randomize the kernel memory sections"
 	depends on X86_64
 	depends on RANDOMIZE_BASE
-	select DYNAMIC_MEMORY_LAYOUT
 	default RANDOMIZE_BASE
 	help
 	  Randomizes the base virtual address of kernel memory sections
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 1faa8f88850a..6b8c8169c71d 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -41,11 +41,7 @@
 #define __PAGE_OFFSET_BASE_L5	_AC(0xff11000000000000, UL)
 #define __PAGE_OFFSET_BASE_L4	_AC(0xffff888000000000, UL)
 
-#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
 #define __PAGE_OFFSET           page_offset_base
-#else
-#define __PAGE_OFFSET           __PAGE_OFFSET_BASE_L4
-#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
 
 #define __START_KERNEL_map	_AC(0xffffffff80000000, UL)
 
diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
index e83721db18c9..eee06f77b245 100644
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -128,15 +128,9 @@ extern unsigned int ptrs_per_p4d;
 #define __VMEMMAP_BASE_L4	0xffffea0000000000UL
 #define __VMEMMAP_BASE_L5	0xffd4000000000000UL
 
-#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
 # define VMALLOC_START		vmalloc_base
 # define VMALLOC_SIZE_TB	(pgtable_l5_enabled() ? VMALLOC_SIZE_TB_L5 : VMALLOC_SIZE_TB_L4)
 # define VMEMMAP_START		vmemmap_base
-#else
-# define VMALLOC_START		__VMALLOC_BASE_L4
-# define VMALLOC_SIZE_TB	VMALLOC_SIZE_TB_L4
-# define VMEMMAP_START		__VMEMMAP_BASE_L4
-#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
 
 #ifdef CONFIG_RANDOMIZE_MEMORY
 # define DIRECT_MAP_PHYSMEM_END	direct_map_physmem_end
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 14f7dda20954..9f617be64fa9 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -59,14 +59,12 @@ unsigned int ptrs_per_p4d __ro_after_init = 1;
 EXPORT_SYMBOL(ptrs_per_p4d);
 #endif
 
-#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
 unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
 EXPORT_SYMBOL(page_offset_base);
 unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4;
 EXPORT_SYMBOL(vmalloc_base);
 unsigned long vmemmap_base __ro_after_init = __VMEMMAP_BASE_L4;
 EXPORT_SYMBOL(vmemmap_base);
-#endif
 
 /* Wipe all early page tables except for the kernel symbol map */
 static void __init reset_early_page_tables(void)
diff --git a/scripts/gdb/linux/pgtable.py b/scripts/gdb/linux/pgtable.py
index 30d837f3dfae..09aac2421fb8 100644
--- a/scripts/gdb/linux/pgtable.py
+++ b/scripts/gdb/linux/pgtable.py
@@ -29,11 +29,9 @@ def page_mask(level=1):
         raise Exception(f'Unknown page level: {level}')
 
 
-#page_offset_base in case CONFIG_DYNAMIC_MEMORY_LAYOUT is disabled
-POB_NO_DYNAMIC_MEM_LAYOUT = '0xffff888000000000'
 def _page_offset_base():
     pob_symbol = gdb.lookup_global_symbol('page_offset_base')
-    pob = pob_symbol.name if pob_symbol else POB_NO_DYNAMIC_MEM_LAYOUT
+    pob = pob_symbol.name
     return gdb.parse_and_eval(pob)
 
 
-- 
2.47.2

[PATCHv2 2/3] x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model

[Kirill A. Shutemov]

5-level paging only supports SPARSEMEM_VMEMMAP. CONFIG_X86_5LEVEL is
being phased out, making 5-level paging support mandatory.

Make CONFIG_SPARSEMEM_VMEMMAP mandatory for x86-64 and eliminate
any associated conditional statements.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
 arch/x86/Kconfig      | 2 +-
 arch/x86/mm/init_64.c | 9 +--------
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d3c2da3b2f0b..45b36a019b5e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1467,7 +1467,6 @@ config X86_PAE
 config X86_5LEVEL
 	bool "Enable 5-level page tables support"
 	default y
-	select SPARSEMEM_VMEMMAP
 	depends on X86_64
 	help
 	  5-level paging enables access to larger address space:
@@ -1579,6 +1578,7 @@ config ARCH_SPARSEMEM_ENABLE
 	def_bool y
 	select SPARSEMEM_STATIC if X86_32
 	select SPARSEMEM_VMEMMAP_ENABLE if X86_64
+	select SPARSEMEM_VMEMMAP if X86_64
 
 config ARCH_SPARSEMEM_DEFAULT
 	def_bool X86_64 || (NUMA && X86_32)
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index bf45c7aed336..66330fe4e18c 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -833,7 +833,6 @@ void __init paging_init(void)
 	zone_sizes_init();
 }
 
-#ifdef CONFIG_SPARSEMEM_VMEMMAP
 #define PAGE_UNUSED 0xFD
 
 /*
@@ -932,7 +931,6 @@ static void __meminit vmemmap_use_new_sub_pmd(unsigned long start, unsigned long
 	if (!IS_ALIGNED(end, PMD_SIZE))
 		unused_pmd_start = end;
 }
-#endif
 
 /*
  * Memory hotplug specific functions
@@ -1152,16 +1150,13 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
 				pmd_clear(pmd);
 				spin_unlock(&init_mm.page_table_lock);
 				pages++;
-			}
-#ifdef CONFIG_SPARSEMEM_VMEMMAP
-			else if (vmemmap_pmd_is_unused(addr, next)) {
+			} else if (vmemmap_pmd_is_unused(addr, next)) {
 					free_hugepage_table(pmd_page(*pmd),
 							    altmap);
 					spin_lock(&init_mm.page_table_lock);
 					pmd_clear(pmd);
 					spin_unlock(&init_mm.page_table_lock);
 			}
-#endif
 			continue;
 		}
 
@@ -1500,7 +1495,6 @@ unsigned long memory_block_size_bytes(void)
 	return memory_block_size_probed;
 }
 
-#ifdef CONFIG_SPARSEMEM_VMEMMAP
 /*
  * Initialise the sparsemem vmemmap using huge-pages at the PMD level.
  */
@@ -1647,4 +1641,3 @@ void __meminit vmemmap_populate_print_last(void)
 		node_start = 0;
 	}
 }
-#endif
-- 
2.47.2

[PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Kirill A. Shutemov]

Both Intel and AMD CPUs support 5-level paging, which is expected to
become more widely adopted in the future.

Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Suggested-by: Borislav Petkov <bp@alien8.de>
---
 Documentation/arch/x86/cpuinfo.rst            |  8 +++----
 .../arch/x86/x86_64/5level-paging.rst         |  9 --------
 arch/x86/Kconfig                              | 22 +------------------
 arch/x86/Kconfig.cpufeatures                  |  4 ----
 arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
 arch/x86/boot/header.S                        |  4 ----
 arch/x86/boot/startup/map_kernel.c            |  5 +----
 arch/x86/include/asm/page_64.h                |  2 --
 arch/x86/include/asm/page_64_types.h          |  7 ------
 arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
 arch/x86/kernel/alternative.c                 |  2 +-
 arch/x86/kernel/head64.c                      |  2 --
 arch/x86/kernel/head_64.S                     |  2 --
 arch/x86/mm/init.c                            |  4 ----
 arch/x86/mm/pgtable.c                         |  2 +-
 drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
 16 files changed, 10 insertions(+), 94 deletions(-)

diff --git a/Documentation/arch/x86/cpuinfo.rst b/Documentation/arch/x86/cpuinfo.rst
index f80e2a558d2a..dd8b7806944e 100644
--- a/Documentation/arch/x86/cpuinfo.rst
+++ b/Documentation/arch/x86/cpuinfo.rst
@@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware.
 The kernel disabled support for it at compile-time
 --------------------------------------------------
 
-For example, if 5-level-paging is not enabled when building (i.e.,
-CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.
+For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,
+CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.
 Even though the feature will still be detected via CPUID, the kernel disables
-it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).
+it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).
 
 The feature is disabled at boot-time
 ------------------------------------
@@ -200,5 +200,3 @@ missing at runtime. For example, AVX flags will not show up if XSAVE feature
 is disabled since they depend on XSAVE feature. Another example would be broken
 CPUs and them missing microcode patches. Due to that, the kernel decides not to
 enable a feature.
-
-.. [#f1] 5-level paging uses linear address of 57 bits.
diff --git a/Documentation/arch/x86/x86_64/5level-paging.rst b/Documentation/arch/x86/x86_64/5level-paging.rst
index 71f882f4a173..ad7ddc13f79d 100644
--- a/Documentation/arch/x86/x86_64/5level-paging.rst
+++ b/Documentation/arch/x86/x86_64/5level-paging.rst
@@ -22,15 +22,6 @@ QEMU 2.9 and later support 5-level paging.
 Virtual memory layout for 5-level paging is described in
 Documentation/arch/x86/x86_64/mm.rst
 
-
-Enabling 5-level paging
-=======================
-CONFIG_X86_5LEVEL=y enables the feature.
-
-Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
-In this case additional page table level -- p4d -- will be folded at
-runtime.
-
 User-space and large virtual address space
 ==========================================
 On x86, 5-level paging enables 56-bit userspace virtual address space.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 45b36a019b5e..7aed3fa0e780 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -427,8 +427,7 @@ config DYNAMIC_PHYSICAL_MASK
 
 config PGTABLE_LEVELS
 	int
-	default 5 if X86_5LEVEL
-	default 4 if X86_64
+	default 5 if X86_64
 	default 3 if X86_PAE
 	default 2
 
@@ -1464,25 +1463,6 @@ config X86_PAE
 	  has the cost of more pagetable lookup overhead, and also
 	  consumes more pagetable space per process.
 
-config X86_5LEVEL
-	bool "Enable 5-level page tables support"
-	default y
-	depends on X86_64
-	help
-	  5-level paging enables access to larger address space:
-	  up to 128 PiB of virtual address space and 4 PiB of
-	  physical address space.
-
-	  It will be supported by future Intel CPUs.
-
-	  A kernel with the option enabled can be booted on machines that
-	  support 4- or 5-level paging.
-
-	  See Documentation/arch/x86/x86_64/5level-paging.rst for more
-	  information.
-
-	  Say N if unsure.
-
 config X86_DIRECT_GBPAGES
 	def_bool y
 	depends on X86_64
diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
index e12d5b7e39a2..250c10627ab3 100644
--- a/arch/x86/Kconfig.cpufeatures
+++ b/arch/x86/Kconfig.cpufeatures
@@ -132,10 +132,6 @@ config X86_DISABLED_FEATURE_OSPKE
 	def_bool y
 	depends on !X86_INTEL_MEMORY_PROTECTION_KEYS
 
-config X86_DISABLED_FEATURE_LA57
-	def_bool y
-	depends on !X86_5LEVEL
-
 config X86_DISABLED_FEATURE_PTI
 	def_bool y
 	depends on !MITIGATION_PAGE_TABLE_ISOLATION
diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index 5a6c7a190e5b..bdd26050dff7 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -10,12 +10,10 @@
 #define BIOS_START_MIN		0x20000U	/* 128K, less than this is insane */
 #define BIOS_START_MAX		0x9f000U	/* 640K, absolute maximum */
 
-#ifdef CONFIG_X86_5LEVEL
 /* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */
 unsigned int __section(".data") __pgtable_l5_enabled;
 unsigned int __section(".data") pgdir_shift = 39;
 unsigned int __section(".data") ptrs_per_p4d = 1;
-#endif
 
 /* Buffer to preserve trampoline memory */
 static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
@@ -114,18 +112,13 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable)
 	 * Check if LA57 is desired and supported.
 	 *
 	 * There are several parts to the check:
-	 *   - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
 	 *   - if user asked to disable 5-level paging: no5lvl in cmdline
 	 *   - if the machine supports 5-level paging:
 	 *     + CPUID leaf 7 is supported
 	 *     + the leaf has the feature bit set
-	 *
-	 * That's substitute for boot_cpu_has() in early boot code.
 	 */
-	if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
-			!cmdline_find_option_bool("no5lvl") &&
-			native_cpuid_eax(0) >= 7 &&
-			(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
+	if (!cmdline_find_option_bool("no5lvl") &&
+	    native_cpuid_eax(0) >= 7 && (native_cpuid_ecx(7) & BIT(16))) {
 		l5_required = true;
 
 		/* Initialize variables for 5-level paging */
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index 9cb91421b4e4..e30649e44d8f 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -361,12 +361,8 @@ xloadflags:
 #endif
 
 #ifdef CONFIG_X86_64
-#ifdef CONFIG_X86_5LEVEL
 #define XLF56 (XLF_5LEVEL|XLF_5LEVEL_ENABLED)
 #else
-#define XLF56 XLF_5LEVEL
-#endif
-#else
 #define XLF56 0
 #endif
 
diff --git a/arch/x86/boot/startup/map_kernel.c b/arch/x86/boot/startup/map_kernel.c
index 905e8734b5a3..332dbe6688c4 100644
--- a/arch/x86/boot/startup/map_kernel.c
+++ b/arch/x86/boot/startup/map_kernel.c
@@ -16,9 +16,6 @@ extern unsigned int next_early_pgt;
 
 static inline bool check_la57_support(void)
 {
-	if (!IS_ENABLED(CONFIG_X86_5LEVEL))
-		return false;
-
 	/*
 	 * 5-level paging is detected and enabled at kernel decompression
 	 * stage. Only check if it has been enabled there.
@@ -129,7 +126,7 @@ unsigned long __head __startup_64(unsigned long p2v_offset,
 	pgd = rip_rel_ptr(early_top_pgt);
 	pgd[pgd_index(__START_KERNEL_map)] += load_delta;
 
-	if (IS_ENABLED(CONFIG_X86_5LEVEL) && la57) {
+	if (la57) {
 		p4d = (p4dval_t *)rip_rel_ptr(level4_kernel_pgt);
 		p4d[MAX_PTRS_PER_P4D - 1] += load_delta;
 
diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h
index d3aab6f4e59a..015d23f3e01f 100644
--- a/arch/x86/include/asm/page_64.h
+++ b/arch/x86/include/asm/page_64.h
@@ -62,7 +62,6 @@ static inline void clear_page(void *page)
 void copy_page(void *to, void *from);
 KCFI_REFERENCE(copy_page);
 
-#ifdef CONFIG_X86_5LEVEL
 /*
  * User space process size.  This is the first address outside the user range.
  * There are a few constraints that determine this:
@@ -93,7 +92,6 @@ static __always_inline unsigned long task_size_max(void)
 
 	return ret;
 }
-#endif	/* CONFIG_X86_5LEVEL */
 
 #endif	/* !__ASSEMBLER__ */
 
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 6b8c8169c71d..7400dab373fe 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -48,14 +48,7 @@
 /* See Documentation/arch/x86/x86_64/mm.rst for a description of the memory map. */
 
 #define __PHYSICAL_MASK_SHIFT	52
-
-#ifdef CONFIG_X86_5LEVEL
 #define __VIRTUAL_MASK_SHIFT	(pgtable_l5_enabled() ? 56 : 47)
-/* See task_size_max() in <asm/page_64.h> */
-#else
-#define __VIRTUAL_MASK_SHIFT	47
-#define task_size_max()		((_AC(1,UL) << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
-#endif
 
 #define TASK_SIZE_MAX		task_size_max()
 #define DEFAULT_MAP_WINDOW	((1UL << 47) - PAGE_SIZE)
diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
index eee06f77b245..4604f924d8b8 100644
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -23,7 +23,6 @@ typedef struct { pmdval_t pmd; } pmd_t;
 
 extern unsigned int __pgtable_l5_enabled;
 
-#ifdef CONFIG_X86_5LEVEL
 #ifdef USE_EARLY_PGTABLE_L5
 /*
  * cpu_feature_enabled() is not available in early boot code.
@@ -37,17 +36,11 @@ static inline bool pgtable_l5_enabled(void)
 #define pgtable_l5_enabled() cpu_feature_enabled(X86_FEATURE_LA57)
 #endif /* USE_EARLY_PGTABLE_L5 */
 
-#else
-#define pgtable_l5_enabled() 0
-#endif /* CONFIG_X86_5LEVEL */
-
 extern unsigned int pgdir_shift;
 extern unsigned int ptrs_per_p4d;
 
 #endif	/* !__ASSEMBLER__ */
 
-#ifdef CONFIG_X86_5LEVEL
-
 /*
  * PGDIR_SHIFT determines what a top-level page table entry can map
  */
@@ -65,17 +58,6 @@ extern unsigned int ptrs_per_p4d;
 
 #define MAX_POSSIBLE_PHYSMEM_BITS	52
 
-#else /* CONFIG_X86_5LEVEL */
-
-/*
- * PGDIR_SHIFT determines what a top-level page table entry can map
- */
-#define PGDIR_SHIFT		39
-#define PTRS_PER_PGD		512
-#define MAX_PTRS_PER_P4D	1
-
-#endif /* CONFIG_X86_5LEVEL */
-
 /*
  * 3rd level page
  */
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 29572927f9c5..ecfe7b497cad 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -596,7 +596,7 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
 	DPRINTK(ALT, "alt table %px, -> %px", start, end);
 
 	/*
-	 * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using
+	 * KASAN_SHADOW_START is defined using
 	 * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
 	 * During the process, KASAN becomes confused seeing partial LA57
 	 * conversion and triggers a false-positive out-of-bound report.
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 9f617be64fa9..533fcf5636fc 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -51,13 +51,11 @@ unsigned int __initdata next_early_pgt;
 SYM_PIC_ALIAS(next_early_pgt);
 pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
 
-#ifdef CONFIG_X86_5LEVEL
 unsigned int __pgtable_l5_enabled __ro_after_init;
 unsigned int pgdir_shift __ro_after_init = 39;
 EXPORT_SYMBOL(pgdir_shift);
 unsigned int ptrs_per_p4d __ro_after_init = 1;
 EXPORT_SYMBOL(ptrs_per_p4d);
-#endif
 
 unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
 EXPORT_SYMBOL(page_offset_base);
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 069420853304..3e9b3a3bd039 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -649,13 +649,11 @@ SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
 SYM_DATA_END(init_top_pgt)
 #endif
 
-#ifdef CONFIG_X86_5LEVEL
 SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
 	.fill	511,8,0
 	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
 SYM_DATA_END(level4_kernel_pgt)
 SYM_PIC_ALIAS(level4_kernel_pgt)
-#endif
 
 SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
 	.fill	L3_START_KERNEL,8,0
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index aa56d9ac0b8f..7456df985d96 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -174,11 +174,7 @@ __ref void *alloc_low_pages(unsigned int num)
  * randomization is enabled.
  */
 
-#ifndef CONFIG_X86_5LEVEL
-#define INIT_PGD_PAGE_TABLES    3
-#else
 #define INIT_PGD_PAGE_TABLES    4
-#endif
 
 #ifndef CONFIG_RANDOMIZE_MEMORY
 #define INIT_PGD_PAGE_COUNT      (2 * INIT_PGD_PAGE_TABLES)
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 59c42dec7076..62777ba4de1a 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -592,7 +592,7 @@ void native_set_fixmap(unsigned /* enum fixed_addresses */ idx,
 }
 
 #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
-#ifdef CONFIG_X86_5LEVEL
+#if CONFIG_PGTABLE_LEVELS > 4
 /**
  * p4d_set_huge - Set up kernel P4D mapping
  * @p4d: Pointer to the P4D entry
diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c
index 77359e802181..f1c5fb45d5f7 100644
--- a/drivers/firmware/efi/libstub/x86-5lvl.c
+++ b/drivers/firmware/efi/libstub/x86-5lvl.c
@@ -62,7 +62,7 @@ efi_status_t efi_setup_5level_paging(void)
 
 void efi_5level_switch(void)
 {
-	bool want_la57 = IS_ENABLED(CONFIG_X86_5LEVEL) && !efi_no5lvl;
+	bool want_la57 = !efi_no5lvl;
 	bool have_la57 = native_read_cr4() & X86_CR4_LA57;
 	bool need_toggle = want_la57 ^ have_la57;
 	u64 *pgt = (void *)la57_toggle + PAGE_SIZE;
-- 
2.47.2

Re: [PATCHv2 1/3] x86/64/mm: Always use dynamic memory layout

[Ard Biesheuvel]

On Fri, 16 May 2025 at 10:15, Kirill A. Shutemov
<kirill.shutemov@linux.intel.com> wrote:
>
> Dynamic memory layout is used by KASLR and 5-level paging.
>
> CONFIG_X86_5LEVEL is going to be removed, making 5-level paging support
> unconditional which requires unconditional support of dynamic memory
> layout.
>
> Remove CONFIG_DYNAMIC_MEMORY_LAYOUT.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

> ---
>  arch/x86/Kconfig                        | 8 --------
>  arch/x86/include/asm/page_64_types.h    | 4 ----
>  arch/x86/include/asm/pgtable_64_types.h | 6 ------
>  arch/x86/kernel/head64.c                | 2 --
>  scripts/gdb/linux/pgtable.py            | 4 +---
>  5 files changed, 1 insertion(+), 23 deletions(-)
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 891a69b308cb..d3c2da3b2f0b 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -1467,7 +1467,6 @@ config X86_PAE
>  config X86_5LEVEL
>         bool "Enable 5-level page tables support"
>         default y
> -       select DYNAMIC_MEMORY_LAYOUT
>         select SPARSEMEM_VMEMMAP
>         depends on X86_64
>         help
> @@ -2167,17 +2166,10 @@ config PHYSICAL_ALIGN
>
>           Don't change this unless you know what you are doing.
>
> -config DYNAMIC_MEMORY_LAYOUT
> -       bool
> -       help
> -         This option makes base addresses of vmalloc and vmemmap as well as
> -         __PAGE_OFFSET movable during boot.
> -
>  config RANDOMIZE_MEMORY
>         bool "Randomize the kernel memory sections"
>         depends on X86_64
>         depends on RANDOMIZE_BASE
> -       select DYNAMIC_MEMORY_LAYOUT
>         default RANDOMIZE_BASE
>         help
>           Randomizes the base virtual address of kernel memory sections
> diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
> index 1faa8f88850a..6b8c8169c71d 100644
> --- a/arch/x86/include/asm/page_64_types.h
> +++ b/arch/x86/include/asm/page_64_types.h
> @@ -41,11 +41,7 @@
>  #define __PAGE_OFFSET_BASE_L5  _AC(0xff11000000000000, UL)
>  #define __PAGE_OFFSET_BASE_L4  _AC(0xffff888000000000, UL)
>
> -#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
>  #define __PAGE_OFFSET           page_offset_base
> -#else
> -#define __PAGE_OFFSET           __PAGE_OFFSET_BASE_L4
> -#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
>
>  #define __START_KERNEL_map     _AC(0xffffffff80000000, UL)
>
> diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
> index e83721db18c9..eee06f77b245 100644
> --- a/arch/x86/include/asm/pgtable_64_types.h
> +++ b/arch/x86/include/asm/pgtable_64_types.h
> @@ -128,15 +128,9 @@ extern unsigned int ptrs_per_p4d;
>  #define __VMEMMAP_BASE_L4      0xffffea0000000000UL
>  #define __VMEMMAP_BASE_L5      0xffd4000000000000UL
>
> -#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
>  # define VMALLOC_START         vmalloc_base
>  # define VMALLOC_SIZE_TB       (pgtable_l5_enabled() ? VMALLOC_SIZE_TB_L5 : VMALLOC_SIZE_TB_L4)
>  # define VMEMMAP_START         vmemmap_base
> -#else
> -# define VMALLOC_START         __VMALLOC_BASE_L4
> -# define VMALLOC_SIZE_TB       VMALLOC_SIZE_TB_L4
> -# define VMEMMAP_START         __VMEMMAP_BASE_L4
> -#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
>
>  #ifdef CONFIG_RANDOMIZE_MEMORY
>  # define DIRECT_MAP_PHYSMEM_END        direct_map_physmem_end
> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> index 14f7dda20954..9f617be64fa9 100644
> --- a/arch/x86/kernel/head64.c
> +++ b/arch/x86/kernel/head64.c
> @@ -59,14 +59,12 @@ unsigned int ptrs_per_p4d __ro_after_init = 1;
>  EXPORT_SYMBOL(ptrs_per_p4d);
>  #endif
>
> -#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
>  unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
>  EXPORT_SYMBOL(page_offset_base);
>  unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4;
>  EXPORT_SYMBOL(vmalloc_base);
>  unsigned long vmemmap_base __ro_after_init = __VMEMMAP_BASE_L4;
>  EXPORT_SYMBOL(vmemmap_base);
> -#endif
>
>  /* Wipe all early page tables except for the kernel symbol map */
>  static void __init reset_early_page_tables(void)
> diff --git a/scripts/gdb/linux/pgtable.py b/scripts/gdb/linux/pgtable.py
> index 30d837f3dfae..09aac2421fb8 100644
> --- a/scripts/gdb/linux/pgtable.py
> +++ b/scripts/gdb/linux/pgtable.py
> @@ -29,11 +29,9 @@ def page_mask(level=1):
>          raise Exception(f'Unknown page level: {level}')
>
>
> -#page_offset_base in case CONFIG_DYNAMIC_MEMORY_LAYOUT is disabled
> -POB_NO_DYNAMIC_MEM_LAYOUT = '0xffff888000000000'
>  def _page_offset_base():
>      pob_symbol = gdb.lookup_global_symbol('page_offset_base')
> -    pob = pob_symbol.name if pob_symbol else POB_NO_DYNAMIC_MEM_LAYOUT
> +    pob = pob_symbol.name
>      return gdb.parse_and_eval(pob)
>
>
> --
> 2.47.2
>
>

Re: [PATCHv2 2/3] x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model

[Ard Biesheuvel]

On Fri, 16 May 2025 at 10:15, Kirill A. Shutemov
<kirill.shutemov@linux.intel.com> wrote:
>
> 5-level paging only supports SPARSEMEM_VMEMMAP. CONFIG_X86_5LEVEL is
> being phased out, making 5-level paging support mandatory.
>
> Make CONFIG_SPARSEMEM_VMEMMAP mandatory for x86-64 and eliminate
> any associated conditional statements.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>

Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

> ---
>  arch/x86/Kconfig      | 2 +-
>  arch/x86/mm/init_64.c | 9 +--------
>  2 files changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index d3c2da3b2f0b..45b36a019b5e 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -1467,7 +1467,6 @@ config X86_PAE
>  config X86_5LEVEL
>         bool "Enable 5-level page tables support"
>         default y
> -       select SPARSEMEM_VMEMMAP
>         depends on X86_64
>         help
>           5-level paging enables access to larger address space:
> @@ -1579,6 +1578,7 @@ config ARCH_SPARSEMEM_ENABLE
>         def_bool y
>         select SPARSEMEM_STATIC if X86_32
>         select SPARSEMEM_VMEMMAP_ENABLE if X86_64
> +       select SPARSEMEM_VMEMMAP if X86_64
>
>  config ARCH_SPARSEMEM_DEFAULT
>         def_bool X86_64 || (NUMA && X86_32)
> diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
> index bf45c7aed336..66330fe4e18c 100644
> --- a/arch/x86/mm/init_64.c
> +++ b/arch/x86/mm/init_64.c
> @@ -833,7 +833,6 @@ void __init paging_init(void)
>         zone_sizes_init();
>  }
>
> -#ifdef CONFIG_SPARSEMEM_VMEMMAP
>  #define PAGE_UNUSED 0xFD
>
>  /*
> @@ -932,7 +931,6 @@ static void __meminit vmemmap_use_new_sub_pmd(unsigned long start, unsigned long
>         if (!IS_ALIGNED(end, PMD_SIZE))
>                 unused_pmd_start = end;
>  }
> -#endif
>
>  /*
>   * Memory hotplug specific functions
> @@ -1152,16 +1150,13 @@ remove_pmd_table(pmd_t *pmd_start, unsigned long addr, unsigned long end,
>                                 pmd_clear(pmd);
>                                 spin_unlock(&init_mm.page_table_lock);
>                                 pages++;
> -                       }
> -#ifdef CONFIG_SPARSEMEM_VMEMMAP
> -                       else if (vmemmap_pmd_is_unused(addr, next)) {
> +                       } else if (vmemmap_pmd_is_unused(addr, next)) {
>                                         free_hugepage_table(pmd_page(*pmd),
>                                                             altmap);
>                                         spin_lock(&init_mm.page_table_lock);
>                                         pmd_clear(pmd);
>                                         spin_unlock(&init_mm.page_table_lock);
>                         }
> -#endif
>                         continue;
>                 }
>
> @@ -1500,7 +1495,6 @@ unsigned long memory_block_size_bytes(void)
>         return memory_block_size_probed;
>  }
>
> -#ifdef CONFIG_SPARSEMEM_VMEMMAP
>  /*
>   * Initialise the sparsemem vmemmap using huge-pages at the PMD level.
>   */
> @@ -1647,4 +1641,3 @@ void __meminit vmemmap_populate_print_last(void)
>                 node_start = 0;
>         }
>  }
> -#endif
> --
> 2.47.2
>

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Ard Biesheuvel]

On Fri, 16 May 2025 at 10:15, Kirill A. Shutemov
<kirill.shutemov@linux.intel.com> wrote:
>
> Both Intel and AMD CPUs support 5-level paging, which is expected to
> become more widely adopted in the future.
>
> Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
>
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Suggested-by: Borislav Petkov <bp@alien8.de>

This will conflict with my changes, but I agree with them in principle so

Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

> ---
>  Documentation/arch/x86/cpuinfo.rst            |  8 +++----
>  .../arch/x86/x86_64/5level-paging.rst         |  9 --------
>  arch/x86/Kconfig                              | 22 +------------------
>  arch/x86/Kconfig.cpufeatures                  |  4 ----
>  arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
>  arch/x86/boot/header.S                        |  4 ----
>  arch/x86/boot/startup/map_kernel.c            |  5 +----
>  arch/x86/include/asm/page_64.h                |  2 --
>  arch/x86/include/asm/page_64_types.h          |  7 ------
>  arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
>  arch/x86/kernel/alternative.c                 |  2 +-
>  arch/x86/kernel/head64.c                      |  2 --
>  arch/x86/kernel/head_64.S                     |  2 --
>  arch/x86/mm/init.c                            |  4 ----
>  arch/x86/mm/pgtable.c                         |  2 +-
>  drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
>  16 files changed, 10 insertions(+), 94 deletions(-)
>
> diff --git a/Documentation/arch/x86/cpuinfo.rst b/Documentation/arch/x86/cpuinfo.rst
> index f80e2a558d2a..dd8b7806944e 100644
> --- a/Documentation/arch/x86/cpuinfo.rst
> +++ b/Documentation/arch/x86/cpuinfo.rst
> @@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware.
>  The kernel disabled support for it at compile-time
>  --------------------------------------------------
>
> -For example, if 5-level-paging is not enabled when building (i.e.,
> -CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.
> +For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,
> +CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.
>  Even though the feature will still be detected via CPUID, the kernel disables
> -it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).
> +it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).
>
>  The feature is disabled at boot-time
>  ------------------------------------
> @@ -200,5 +200,3 @@ missing at runtime. For example, AVX flags will not show up if XSAVE feature
>  is disabled since they depend on XSAVE feature. Another example would be broken
>  CPUs and them missing microcode patches. Due to that, the kernel decides not to
>  enable a feature.
> -
> -.. [#f1] 5-level paging uses linear address of 57 bits.
> diff --git a/Documentation/arch/x86/x86_64/5level-paging.rst b/Documentation/arch/x86/x86_64/5level-paging.rst
> index 71f882f4a173..ad7ddc13f79d 100644
> --- a/Documentation/arch/x86/x86_64/5level-paging.rst
> +++ b/Documentation/arch/x86/x86_64/5level-paging.rst
> @@ -22,15 +22,6 @@ QEMU 2.9 and later support 5-level paging.
>  Virtual memory layout for 5-level paging is described in
>  Documentation/arch/x86/x86_64/mm.rst
>
> -
> -Enabling 5-level paging
> -=======================
> -CONFIG_X86_5LEVEL=y enables the feature.
> -
> -Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
> -In this case additional page table level -- p4d -- will be folded at
> -runtime.
> -
>  User-space and large virtual address space
>  ==========================================
>  On x86, 5-level paging enables 56-bit userspace virtual address space.
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 45b36a019b5e..7aed3fa0e780 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -427,8 +427,7 @@ config DYNAMIC_PHYSICAL_MASK
>
>  config PGTABLE_LEVELS
>         int
> -       default 5 if X86_5LEVEL
> -       default 4 if X86_64
> +       default 5 if X86_64
>         default 3 if X86_PAE
>         default 2
>
> @@ -1464,25 +1463,6 @@ config X86_PAE
>           has the cost of more pagetable lookup overhead, and also
>           consumes more pagetable space per process.
>
> -config X86_5LEVEL
> -       bool "Enable 5-level page tables support"
> -       default y
> -       depends on X86_64
> -       help
> -         5-level paging enables access to larger address space:
> -         up to 128 PiB of virtual address space and 4 PiB of
> -         physical address space.
> -
> -         It will be supported by future Intel CPUs.
> -
> -         A kernel with the option enabled can be booted on machines that
> -         support 4- or 5-level paging.
> -
> -         See Documentation/arch/x86/x86_64/5level-paging.rst for more
> -         information.
> -
> -         Say N if unsure.
> -
>  config X86_DIRECT_GBPAGES
>         def_bool y
>         depends on X86_64
> diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
> index e12d5b7e39a2..250c10627ab3 100644
> --- a/arch/x86/Kconfig.cpufeatures
> +++ b/arch/x86/Kconfig.cpufeatures
> @@ -132,10 +132,6 @@ config X86_DISABLED_FEATURE_OSPKE
>         def_bool y
>         depends on !X86_INTEL_MEMORY_PROTECTION_KEYS
>
> -config X86_DISABLED_FEATURE_LA57
> -       def_bool y
> -       depends on !X86_5LEVEL
> -
>  config X86_DISABLED_FEATURE_PTI
>         def_bool y
>         depends on !MITIGATION_PAGE_TABLE_ISOLATION
> diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
> index 5a6c7a190e5b..bdd26050dff7 100644
> --- a/arch/x86/boot/compressed/pgtable_64.c
> +++ b/arch/x86/boot/compressed/pgtable_64.c
> @@ -10,12 +10,10 @@
>  #define BIOS_START_MIN         0x20000U        /* 128K, less than this is insane */
>  #define BIOS_START_MAX         0x9f000U        /* 640K, absolute maximum */
>
> -#ifdef CONFIG_X86_5LEVEL
>  /* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */
>  unsigned int __section(".data") __pgtable_l5_enabled;
>  unsigned int __section(".data") pgdir_shift = 39;
>  unsigned int __section(".data") ptrs_per_p4d = 1;
> -#endif
>
>  /* Buffer to preserve trampoline memory */
>  static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
> @@ -114,18 +112,13 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable)
>          * Check if LA57 is desired and supported.
>          *
>          * There are several parts to the check:
> -        *   - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
>          *   - if user asked to disable 5-level paging: no5lvl in cmdline
>          *   - if the machine supports 5-level paging:
>          *     + CPUID leaf 7 is supported
>          *     + the leaf has the feature bit set
> -        *
> -        * That's substitute for boot_cpu_has() in early boot code.
>          */
> -       if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
> -                       !cmdline_find_option_bool("no5lvl") &&
> -                       native_cpuid_eax(0) >= 7 &&
> -                       (native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
> +       if (!cmdline_find_option_bool("no5lvl") &&
> +           native_cpuid_eax(0) >= 7 && (native_cpuid_ecx(7) & BIT(16))) {
>                 l5_required = true;
>
>                 /* Initialize variables for 5-level paging */
> diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
> index 9cb91421b4e4..e30649e44d8f 100644
> --- a/arch/x86/boot/header.S
> +++ b/arch/x86/boot/header.S
> @@ -361,12 +361,8 @@ xloadflags:
>  #endif
>
>  #ifdef CONFIG_X86_64
> -#ifdef CONFIG_X86_5LEVEL
>  #define XLF56 (XLF_5LEVEL|XLF_5LEVEL_ENABLED)
>  #else
> -#define XLF56 XLF_5LEVEL
> -#endif
> -#else
>  #define XLF56 0
>  #endif
>
> diff --git a/arch/x86/boot/startup/map_kernel.c b/arch/x86/boot/startup/map_kernel.c
> index 905e8734b5a3..332dbe6688c4 100644
> --- a/arch/x86/boot/startup/map_kernel.c
> +++ b/arch/x86/boot/startup/map_kernel.c
> @@ -16,9 +16,6 @@ extern unsigned int next_early_pgt;
>
>  static inline bool check_la57_support(void)
>  {
> -       if (!IS_ENABLED(CONFIG_X86_5LEVEL))
> -               return false;
> -
>         /*
>          * 5-level paging is detected and enabled at kernel decompression
>          * stage. Only check if it has been enabled there.
> @@ -129,7 +126,7 @@ unsigned long __head __startup_64(unsigned long p2v_offset,
>         pgd = rip_rel_ptr(early_top_pgt);
>         pgd[pgd_index(__START_KERNEL_map)] += load_delta;
>
> -       if (IS_ENABLED(CONFIG_X86_5LEVEL) && la57) {
> +       if (la57) {
>                 p4d = (p4dval_t *)rip_rel_ptr(level4_kernel_pgt);
>                 p4d[MAX_PTRS_PER_P4D - 1] += load_delta;
>
> diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h
> index d3aab6f4e59a..015d23f3e01f 100644
> --- a/arch/x86/include/asm/page_64.h
> +++ b/arch/x86/include/asm/page_64.h
> @@ -62,7 +62,6 @@ static inline void clear_page(void *page)
>  void copy_page(void *to, void *from);
>  KCFI_REFERENCE(copy_page);
>
> -#ifdef CONFIG_X86_5LEVEL
>  /*
>   * User space process size.  This is the first address outside the user range.
>   * There are a few constraints that determine this:
> @@ -93,7 +92,6 @@ static __always_inline unsigned long task_size_max(void)
>
>         return ret;
>  }
> -#endif /* CONFIG_X86_5LEVEL */
>
>  #endif /* !__ASSEMBLER__ */
>
> diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
> index 6b8c8169c71d..7400dab373fe 100644
> --- a/arch/x86/include/asm/page_64_types.h
> +++ b/arch/x86/include/asm/page_64_types.h
> @@ -48,14 +48,7 @@
>  /* See Documentation/arch/x86/x86_64/mm.rst for a description of the memory map. */
>
>  #define __PHYSICAL_MASK_SHIFT  52
> -
> -#ifdef CONFIG_X86_5LEVEL
>  #define __VIRTUAL_MASK_SHIFT   (pgtable_l5_enabled() ? 56 : 47)
> -/* See task_size_max() in <asm/page_64.h> */
> -#else
> -#define __VIRTUAL_MASK_SHIFT   47
> -#define task_size_max()                ((_AC(1,UL) << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
> -#endif
>
>  #define TASK_SIZE_MAX          task_size_max()
>  #define DEFAULT_MAP_WINDOW     ((1UL << 47) - PAGE_SIZE)
> diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
> index eee06f77b245..4604f924d8b8 100644
> --- a/arch/x86/include/asm/pgtable_64_types.h
> +++ b/arch/x86/include/asm/pgtable_64_types.h
> @@ -23,7 +23,6 @@ typedef struct { pmdval_t pmd; } pmd_t;
>
>  extern unsigned int __pgtable_l5_enabled;
>
> -#ifdef CONFIG_X86_5LEVEL
>  #ifdef USE_EARLY_PGTABLE_L5
>  /*
>   * cpu_feature_enabled() is not available in early boot code.
> @@ -37,17 +36,11 @@ static inline bool pgtable_l5_enabled(void)
>  #define pgtable_l5_enabled() cpu_feature_enabled(X86_FEATURE_LA57)
>  #endif /* USE_EARLY_PGTABLE_L5 */
>
> -#else
> -#define pgtable_l5_enabled() 0
> -#endif /* CONFIG_X86_5LEVEL */
> -
>  extern unsigned int pgdir_shift;
>  extern unsigned int ptrs_per_p4d;
>
>  #endif /* !__ASSEMBLER__ */
>
> -#ifdef CONFIG_X86_5LEVEL
> -
>  /*
>   * PGDIR_SHIFT determines what a top-level page table entry can map
>   */
> @@ -65,17 +58,6 @@ extern unsigned int ptrs_per_p4d;
>
>  #define MAX_POSSIBLE_PHYSMEM_BITS      52
>
> -#else /* CONFIG_X86_5LEVEL */
> -
> -/*
> - * PGDIR_SHIFT determines what a top-level page table entry can map
> - */
> -#define PGDIR_SHIFT            39
> -#define PTRS_PER_PGD           512
> -#define MAX_PTRS_PER_P4D       1
> -
> -#endif /* CONFIG_X86_5LEVEL */
> -
>  /*
>   * 3rd level page
>   */
> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
> index 29572927f9c5..ecfe7b497cad 100644
> --- a/arch/x86/kernel/alternative.c
> +++ b/arch/x86/kernel/alternative.c
> @@ -596,7 +596,7 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
>         DPRINTK(ALT, "alt table %px, -> %px", start, end);
>
>         /*
> -        * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using
> +        * KASAN_SHADOW_START is defined using
>          * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
>          * During the process, KASAN becomes confused seeing partial LA57
>          * conversion and triggers a false-positive out-of-bound report.
> diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
> index 9f617be64fa9..533fcf5636fc 100644
> --- a/arch/x86/kernel/head64.c
> +++ b/arch/x86/kernel/head64.c
> @@ -51,13 +51,11 @@ unsigned int __initdata next_early_pgt;
>  SYM_PIC_ALIAS(next_early_pgt);
>  pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
>
> -#ifdef CONFIG_X86_5LEVEL
>  unsigned int __pgtable_l5_enabled __ro_after_init;
>  unsigned int pgdir_shift __ro_after_init = 39;
>  EXPORT_SYMBOL(pgdir_shift);
>  unsigned int ptrs_per_p4d __ro_after_init = 1;
>  EXPORT_SYMBOL(ptrs_per_p4d);
> -#endif
>
>  unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
>  EXPORT_SYMBOL(page_offset_base);
> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
> index 069420853304..3e9b3a3bd039 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -649,13 +649,11 @@ SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
>  SYM_DATA_END(init_top_pgt)
>  #endif
>
> -#ifdef CONFIG_X86_5LEVEL
>  SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
>         .fill   511,8,0
>         .quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
>  SYM_DATA_END(level4_kernel_pgt)
>  SYM_PIC_ALIAS(level4_kernel_pgt)
> -#endif
>
>  SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
>         .fill   L3_START_KERNEL,8,0
> diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
> index aa56d9ac0b8f..7456df985d96 100644
> --- a/arch/x86/mm/init.c
> +++ b/arch/x86/mm/init.c
> @@ -174,11 +174,7 @@ __ref void *alloc_low_pages(unsigned int num)
>   * randomization is enabled.
>   */
>
> -#ifndef CONFIG_X86_5LEVEL
> -#define INIT_PGD_PAGE_TABLES    3
> -#else
>  #define INIT_PGD_PAGE_TABLES    4
> -#endif
>
>  #ifndef CONFIG_RANDOMIZE_MEMORY
>  #define INIT_PGD_PAGE_COUNT      (2 * INIT_PGD_PAGE_TABLES)
> diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
> index 59c42dec7076..62777ba4de1a 100644
> --- a/arch/x86/mm/pgtable.c
> +++ b/arch/x86/mm/pgtable.c
> @@ -592,7 +592,7 @@ void native_set_fixmap(unsigned /* enum fixed_addresses */ idx,
>  }
>
>  #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
> -#ifdef CONFIG_X86_5LEVEL
> +#if CONFIG_PGTABLE_LEVELS > 4
>  /**
>   * p4d_set_huge - Set up kernel P4D mapping
>   * @p4d: Pointer to the P4D entry
> diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c
> index 77359e802181..f1c5fb45d5f7 100644
> --- a/drivers/firmware/efi/libstub/x86-5lvl.c
> +++ b/drivers/firmware/efi/libstub/x86-5lvl.c
> @@ -62,7 +62,7 @@ efi_status_t efi_setup_5level_paging(void)
>
>  void efi_5level_switch(void)
>  {
> -       bool want_la57 = IS_ENABLED(CONFIG_X86_5LEVEL) && !efi_no5lvl;
> +       bool want_la57 = !efi_no5lvl;
>         bool have_la57 = native_read_cr4() & X86_CR4_LA57;
>         bool need_toggle = want_la57 ^ have_la57;
>         u64 *pgt = (void *)la57_toggle + PAGE_SIZE;
> --
> 2.47.2
>

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Jürgen Groß]

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On 16.05.25 11:15, Kirill A. Shutemov wrote:
> Both Intel and AMD CPUs support 5-level paging, which is expected to
> become more widely adopted in the future.
> 
> Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
> 
> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> Suggested-by: Borislav Petkov <bp@alien8.de>
> ---
>   Documentation/arch/x86/cpuinfo.rst            |  8 +++----
>   .../arch/x86/x86_64/5level-paging.rst         |  9 --------
>   arch/x86/Kconfig                              | 22 +------------------
>   arch/x86/Kconfig.cpufeatures                  |  4 ----
>   arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
>   arch/x86/boot/header.S                        |  4 ----
>   arch/x86/boot/startup/map_kernel.c            |  5 +----
>   arch/x86/include/asm/page_64.h                |  2 --
>   arch/x86/include/asm/page_64_types.h          |  7 ------
>   arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
>   arch/x86/kernel/alternative.c                 |  2 +-
>   arch/x86/kernel/head64.c                      |  2 --
>   arch/x86/kernel/head_64.S                     |  2 --
>   arch/x86/mm/init.c                            |  4 ----
>   arch/x86/mm/pgtable.c                         |  2 +-
>   drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
>   16 files changed, 10 insertions(+), 94 deletions(-)

There are some instances of:

#if CONFIG_PGTABLE_LEVELS >= 5

in 64-bit-only code under arch/x86, which could be simplified, too.

They are still correct, but I wanted to hint at further code removals
being possible.


Juergen

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Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Kirill A. Shutemov]

On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote:
> On 16.05.25 11:15, Kirill A. Shutemov wrote:
> > Both Intel and AMD CPUs support 5-level paging, which is expected to
> > become more widely adopted in the future.
> > 
> > Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
> > 
> > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> > Suggested-by: Borislav Petkov <bp@alien8.de>
> > ---
> >   Documentation/arch/x86/cpuinfo.rst            |  8 +++----
> >   .../arch/x86/x86_64/5level-paging.rst         |  9 --------
> >   arch/x86/Kconfig                              | 22 +------------------
> >   arch/x86/Kconfig.cpufeatures                  |  4 ----
> >   arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
> >   arch/x86/boot/header.S                        |  4 ----
> >   arch/x86/boot/startup/map_kernel.c            |  5 +----
> >   arch/x86/include/asm/page_64.h                |  2 --
> >   arch/x86/include/asm/page_64_types.h          |  7 ------
> >   arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
> >   arch/x86/kernel/alternative.c                 |  2 +-
> >   arch/x86/kernel/head64.c                      |  2 --
> >   arch/x86/kernel/head_64.S                     |  2 --
> >   arch/x86/mm/init.c                            |  4 ----
> >   arch/x86/mm/pgtable.c                         |  2 +-
> >   drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
> >   16 files changed, 10 insertions(+), 94 deletions(-)
> 
> There are some instances of:
> 
> #if CONFIG_PGTABLE_LEVELS >= 5
> 
> in 64-bit-only code under arch/x86, which could be simplified, too.
> 
> They are still correct, but I wanted to hint at further code removals
> being possible.

Okay, fair enough. Fixup is below.

Did I miss anything else?

diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c
index 2fb7d53cf333..c9103a6fa06e 100644
--- a/arch/x86/entry/vsyscall/vsyscall_64.c
+++ b/arch/x86/entry/vsyscall/vsyscall_64.c
@@ -341,9 +341,7 @@ void __init set_vsyscall_pgtable_user_bits(pgd_t *root)
 	pgd = pgd_offset_pgd(root, VSYSCALL_ADDR);
 	set_pgd(pgd, __pgd(pgd_val(*pgd) | _PAGE_USER));
 	p4d = p4d_offset(pgd, VSYSCALL_ADDR);
-#if CONFIG_PGTABLE_LEVELS >= 5
 	set_p4d(p4d, __p4d(p4d_val(*p4d) | _PAGE_USER));
-#endif
 	pud = pud_offset(p4d, VSYSCALL_ADDR);
 	set_pud(pud, __pud(pud_val(*pud) | _PAGE_USER));
 	pmd = pmd_offset(pud, VSYSCALL_ADDR);
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index b89f8f1194a9..f06e5d6a2747 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -41,11 +41,9 @@ static inline void sync_initial_page_table(void) { }
 	pr_err("%s:%d: bad pud %p(%016lx)\n",		\
 	       __FILE__, __LINE__, &(e), pud_val(e))
 
-#if CONFIG_PGTABLE_LEVELS >= 5
 #define p4d_ERROR(e)					\
 	pr_err("%s:%d: bad p4d %p(%016lx)\n",		\
 	       __FILE__, __LINE__, &(e), p4d_val(e))
-#endif
 
 #define pgd_ERROR(e)					\
 	pr_err("%s:%d: bad pgd %p(%016lx)\n",		\
diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
index 38971c6dcd4b..61c52bb80e33 100644
--- a/arch/x86/xen/mmu_pv.c
+++ b/arch/x86/xen/mmu_pv.c
@@ -578,7 +578,6 @@ static void xen_set_p4d(p4d_t *ptr, p4d_t val)
 	xen_mc_issue(XEN_LAZY_MMU);
 }
 
-#if CONFIG_PGTABLE_LEVELS >= 5
 __visible p4dval_t xen_p4d_val(p4d_t p4d)
 {
 	return pte_mfn_to_pfn(p4d.p4d);
@@ -592,7 +591,6 @@ __visible p4d_t xen_make_p4d(p4dval_t p4d)
 	return native_make_p4d(p4d);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_p4d);
-#endif  /* CONFIG_PGTABLE_LEVELS >= 5 */
 
 static void xen_pmd_walk(struct mm_struct *mm, pmd_t *pmd,
 			 void (*func)(struct mm_struct *mm, struct page *,
-- 
  Kiryl Shutsemau / Kirill A. Shutemov

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Jürgen Groß]

[-- Attachment #1.1.1: Type: text/plain, Size: 4235 bytes --]

On 16.05.25 13:09, Kirill A. Shutemov wrote:
> On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote:
>> On 16.05.25 11:15, Kirill A. Shutemov wrote:
>>> Both Intel and AMD CPUs support 5-level paging, which is expected to
>>> become more widely adopted in the future.
>>>
>>> Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
>>>
>>> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
>>> Suggested-by: Borislav Petkov <bp@alien8.de>
>>> ---
>>>    Documentation/arch/x86/cpuinfo.rst            |  8 +++----
>>>    .../arch/x86/x86_64/5level-paging.rst         |  9 --------
>>>    arch/x86/Kconfig                              | 22 +------------------
>>>    arch/x86/Kconfig.cpufeatures                  |  4 ----
>>>    arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
>>>    arch/x86/boot/header.S                        |  4 ----
>>>    arch/x86/boot/startup/map_kernel.c            |  5 +----
>>>    arch/x86/include/asm/page_64.h                |  2 --
>>>    arch/x86/include/asm/page_64_types.h          |  7 ------
>>>    arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
>>>    arch/x86/kernel/alternative.c                 |  2 +-
>>>    arch/x86/kernel/head64.c                      |  2 --
>>>    arch/x86/kernel/head_64.S                     |  2 --
>>>    arch/x86/mm/init.c                            |  4 ----
>>>    arch/x86/mm/pgtable.c                         |  2 +-
>>>    drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
>>>    16 files changed, 10 insertions(+), 94 deletions(-)
>>
>> There are some instances of:
>>
>> #if CONFIG_PGTABLE_LEVELS >= 5
>>
>> in 64-bit-only code under arch/x86, which could be simplified, too.
>>
>> They are still correct, but I wanted to hint at further code removals
>> being possible.
> 
> Okay, fair enough. Fixup is below.
> 
> Did I miss anything else?

Yes.

One more instance in arch/x86/xen/mmu_pv.c,
one in arch/x86/include/asm/paravirt.h,
one in arch/x86/include/asm/paravirt_types.h,
one in arch/x86/kernel/paravirt.c


Juergen

> 
> diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c
> index 2fb7d53cf333..c9103a6fa06e 100644
> --- a/arch/x86/entry/vsyscall/vsyscall_64.c
> +++ b/arch/x86/entry/vsyscall/vsyscall_64.c
> @@ -341,9 +341,7 @@ void __init set_vsyscall_pgtable_user_bits(pgd_t *root)
>   	pgd = pgd_offset_pgd(root, VSYSCALL_ADDR);
>   	set_pgd(pgd, __pgd(pgd_val(*pgd) | _PAGE_USER));
>   	p4d = p4d_offset(pgd, VSYSCALL_ADDR);
> -#if CONFIG_PGTABLE_LEVELS >= 5
>   	set_p4d(p4d, __p4d(p4d_val(*p4d) | _PAGE_USER));
> -#endif
>   	pud = pud_offset(p4d, VSYSCALL_ADDR);
>   	set_pud(pud, __pud(pud_val(*pud) | _PAGE_USER));
>   	pmd = pmd_offset(pud, VSYSCALL_ADDR);
> diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
> index b89f8f1194a9..f06e5d6a2747 100644
> --- a/arch/x86/include/asm/pgtable_64.h
> +++ b/arch/x86/include/asm/pgtable_64.h
> @@ -41,11 +41,9 @@ static inline void sync_initial_page_table(void) { }
>   	pr_err("%s:%d: bad pud %p(%016lx)\n",		\
>   	       __FILE__, __LINE__, &(e), pud_val(e))
>   
> -#if CONFIG_PGTABLE_LEVELS >= 5
>   #define p4d_ERROR(e)					\
>   	pr_err("%s:%d: bad p4d %p(%016lx)\n",		\
>   	       __FILE__, __LINE__, &(e), p4d_val(e))
> -#endif
>   
>   #define pgd_ERROR(e)					\
>   	pr_err("%s:%d: bad pgd %p(%016lx)\n",		\
> diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
> index 38971c6dcd4b..61c52bb80e33 100644
> --- a/arch/x86/xen/mmu_pv.c
> +++ b/arch/x86/xen/mmu_pv.c
> @@ -578,7 +578,6 @@ static void xen_set_p4d(p4d_t *ptr, p4d_t val)
>   	xen_mc_issue(XEN_LAZY_MMU);
>   }
>   
> -#if CONFIG_PGTABLE_LEVELS >= 5
>   __visible p4dval_t xen_p4d_val(p4d_t p4d)
>   {
>   	return pte_mfn_to_pfn(p4d.p4d);
> @@ -592,7 +591,6 @@ __visible p4d_t xen_make_p4d(p4dval_t p4d)
>   	return native_make_p4d(p4d);
>   }
>   PV_CALLEE_SAVE_REGS_THUNK(xen_make_p4d);
> -#endif  /* CONFIG_PGTABLE_LEVELS >= 5 */
>   
>   static void xen_pmd_walk(struct mm_struct *mm, pmd_t *pmd,
>   			 void (*func)(struct mm_struct *mm, struct page *,


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Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Kirill A. Shutemov]

On Fri, May 16, 2025 at 01:29:27PM +0200, Jürgen Groß wrote:
> On 16.05.25 13:09, Kirill A. Shutemov wrote:
> > On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote:
> > > On 16.05.25 11:15, Kirill A. Shutemov wrote:
> > > > Both Intel and AMD CPUs support 5-level paging, which is expected to
> > > > become more widely adopted in the future.
> > > > 
> > > > Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
> > > > 
> > > > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> > > > Suggested-by: Borislav Petkov <bp@alien8.de>
> > > > ---
> > > >    Documentation/arch/x86/cpuinfo.rst            |  8 +++----
> > > >    .../arch/x86/x86_64/5level-paging.rst         |  9 --------
> > > >    arch/x86/Kconfig                              | 22 +------------------
> > > >    arch/x86/Kconfig.cpufeatures                  |  4 ----
> > > >    arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
> > > >    arch/x86/boot/header.S                        |  4 ----
> > > >    arch/x86/boot/startup/map_kernel.c            |  5 +----
> > > >    arch/x86/include/asm/page_64.h                |  2 --
> > > >    arch/x86/include/asm/page_64_types.h          |  7 ------
> > > >    arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
> > > >    arch/x86/kernel/alternative.c                 |  2 +-
> > > >    arch/x86/kernel/head64.c                      |  2 --
> > > >    arch/x86/kernel/head_64.S                     |  2 --
> > > >    arch/x86/mm/init.c                            |  4 ----
> > > >    arch/x86/mm/pgtable.c                         |  2 +-
> > > >    drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
> > > >    16 files changed, 10 insertions(+), 94 deletions(-)
> > > 
> > > There are some instances of:
> > > 
> > > #if CONFIG_PGTABLE_LEVELS >= 5
> > > 
> > > in 64-bit-only code under arch/x86, which could be simplified, too.
> > > 
> > > They are still correct, but I wanted to hint at further code removals
> > > being possible.
> > 
> > Okay, fair enough. Fixup is below.
> > 
> > Did I miss anything else?
> 
> Yes.
> 
> One more instance in arch/x86/xen/mmu_pv.c,

Ah. Right.

> one in arch/x86/include/asm/paravirt.h,
> one in arch/x86/include/asm/paravirt_types.h,
> one in arch/x86/kernel/paravirt.c

Hm. Is paravirt 64-bit only?

-- 
  Kiryl Shutsemau / Kirill A. Shutemov

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Juergen Gross]

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On 16.05.25 13:47, Kirill A. Shutemov wrote:
> On Fri, May 16, 2025 at 01:29:27PM +0200, Jürgen Groß wrote:
>> On 16.05.25 13:09, Kirill A. Shutemov wrote:
>>> On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote:
>>>> On 16.05.25 11:15, Kirill A. Shutemov wrote:
>>>>> Both Intel and AMD CPUs support 5-level paging, which is expected to
>>>>> become more widely adopted in the future.
>>>>>
>>>>> Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
>>>>>
>>>>> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
>>>>> Suggested-by: Borislav Petkov <bp@alien8.de>
>>>>> ---
>>>>>     Documentation/arch/x86/cpuinfo.rst            |  8 +++----
>>>>>     .../arch/x86/x86_64/5level-paging.rst         |  9 --------
>>>>>     arch/x86/Kconfig                              | 22 +------------------
>>>>>     arch/x86/Kconfig.cpufeatures                  |  4 ----
>>>>>     arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
>>>>>     arch/x86/boot/header.S                        |  4 ----
>>>>>     arch/x86/boot/startup/map_kernel.c            |  5 +----
>>>>>     arch/x86/include/asm/page_64.h                |  2 --
>>>>>     arch/x86/include/asm/page_64_types.h          |  7 ------
>>>>>     arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
>>>>>     arch/x86/kernel/alternative.c                 |  2 +-
>>>>>     arch/x86/kernel/head64.c                      |  2 --
>>>>>     arch/x86/kernel/head_64.S                     |  2 --
>>>>>     arch/x86/mm/init.c                            |  4 ----
>>>>>     arch/x86/mm/pgtable.c                         |  2 +-
>>>>>     drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
>>>>>     16 files changed, 10 insertions(+), 94 deletions(-)
>>>>
>>>> There are some instances of:
>>>>
>>>> #if CONFIG_PGTABLE_LEVELS >= 5
>>>>
>>>> in 64-bit-only code under arch/x86, which could be simplified, too.
>>>>
>>>> They are still correct, but I wanted to hint at further code removals
>>>> being possible.
>>>
>>> Okay, fair enough. Fixup is below.
>>>
>>> Did I miss anything else?
>>
>> Yes.
>>
>> One more instance in arch/x86/xen/mmu_pv.c,
> 
> Ah. Right.
> 
>> one in arch/x86/include/asm/paravirt.h,
>> one in arch/x86/include/asm/paravirt_types.h,
>> one in arch/x86/kernel/paravirt.c
> 
> Hm. Is paravirt 64-bit only?
> 

CONFIG_PARAVIRT_XXL is.


Juergen

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Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Kirill A. Shutemov]

On Fri, May 16, 2025 at 02:47:46PM +0300, Kirill A. Shutemov wrote:
> On Fri, May 16, 2025 at 01:29:27PM +0200, Jürgen Groß wrote:
> > On 16.05.25 13:09, Kirill A. Shutemov wrote:
> > > On Fri, May 16, 2025 at 12:42:21PM +0200, Jürgen Groß wrote:
> > > > On 16.05.25 11:15, Kirill A. Shutemov wrote:
> > > > > Both Intel and AMD CPUs support 5-level paging, which is expected to
> > > > > become more widely adopted in the future.
> > > > > 
> > > > > Remove CONFIG_X86_5LEVEL and ifdeffery for it to make it more readable.
> > > > > 
> > > > > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> > > > > Suggested-by: Borislav Petkov <bp@alien8.de>
> > > > > ---
> > > > >    Documentation/arch/x86/cpuinfo.rst            |  8 +++----
> > > > >    .../arch/x86/x86_64/5level-paging.rst         |  9 --------
> > > > >    arch/x86/Kconfig                              | 22 +------------------
> > > > >    arch/x86/Kconfig.cpufeatures                  |  4 ----
> > > > >    arch/x86/boot/compressed/pgtable_64.c         | 11 ++--------
> > > > >    arch/x86/boot/header.S                        |  4 ----
> > > > >    arch/x86/boot/startup/map_kernel.c            |  5 +----
> > > > >    arch/x86/include/asm/page_64.h                |  2 --
> > > > >    arch/x86/include/asm/page_64_types.h          |  7 ------
> > > > >    arch/x86/include/asm/pgtable_64_types.h       | 18 ---------------
> > > > >    arch/x86/kernel/alternative.c                 |  2 +-
> > > > >    arch/x86/kernel/head64.c                      |  2 --
> > > > >    arch/x86/kernel/head_64.S                     |  2 --
> > > > >    arch/x86/mm/init.c                            |  4 ----
> > > > >    arch/x86/mm/pgtable.c                         |  2 +-
> > > > >    drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
> > > > >    16 files changed, 10 insertions(+), 94 deletions(-)
> > > > 
> > > > There are some instances of:
> > > > 
> > > > #if CONFIG_PGTABLE_LEVELS >= 5
> > > > 
> > > > in 64-bit-only code under arch/x86, which could be simplified, too.
> > > > 
> > > > They are still correct, but I wanted to hint at further code removals
> > > > being possible.
> > > 
> > > Okay, fair enough. Fixup is below.
> > > 
> > > Did I miss anything else?
> > 
> > Yes.
> > 
> > One more instance in arch/x86/xen/mmu_pv.c,
> 
> Ah. Right.
> 
> > one in arch/x86/include/asm/paravirt.h,
> > one in arch/x86/include/asm/paravirt_types.h,
> > one in arch/x86/kernel/paravirt.c
> 
> Hm. Is paravirt 64-bit only?

Oh. It is PARAVIRT_XXL thingy which is only used by XEN_PV which is 64-bit
only, right?

Do we want to make PARAVIRT_XXL explicitly 64-bit only?

-- 
  Kiryl Shutsemau / Kirill A. Shutemov

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Borislav Petkov]

On Fri, May 16, 2025 at 12:15:33PM +0300, Kirill A. Shutemov wrote:
> @@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware.
>  The kernel disabled support for it at compile-time
>  --------------------------------------------------
>  
> -For example, if 5-level-paging is not enabled when building (i.e.,
> -CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.
> +For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,
> +CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.
>  Even though the feature will still be detected via CPUID, the kernel disables
> -it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).
> +it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).

LOL, good one.

The rest looks nice and good to me. And FWIW, it boots fine on my Zen5 with
5lvl enabled.

Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Ingo Molnar]

* Borislav Petkov <bp@alien8.de> wrote:

> On Fri, May 16, 2025 at 12:15:33PM +0300, Kirill A. Shutemov wrote:
> > @@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware.
> >  The kernel disabled support for it at compile-time
> >  --------------------------------------------------
> >  
> > -For example, if 5-level-paging is not enabled when building (i.e.,
> > -CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.
> > +For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,
> > +CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.
> >  Even though the feature will still be detected via CPUID, the kernel disables
> > -it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).
> > +it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).
> 
> LOL, good one.
> 
> The rest looks nice and good to me. And FWIW, it boots fine on my Zen5 with
> 5lvl enabled.
> 
> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>

What's your preference on timing? v6.17 or v6.16?

Thanks,

	Ingo

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Borislav Petkov]

On Fri, May 16, 2025 at 05:46:51PM +0200, Ingo Molnar wrote:
> 
> * Borislav Petkov <bp@alien8.de> wrote:
> 
> > On Fri, May 16, 2025 at 12:15:33PM +0300, Kirill A. Shutemov wrote:
> > > @@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware.
> > >  The kernel disabled support for it at compile-time
> > >  --------------------------------------------------
> > >  
> > > -For example, if 5-level-paging is not enabled when building (i.e.,
> > > -CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.
> > > +For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,
> > > +CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.
> > >  Even though the feature will still be detected via CPUID, the kernel disables
> > > -it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).
> > > +it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).
> > 
> > LOL, good one.
> > 
> > The rest looks nice and good to me. And FWIW, it boots fine on my Zen5 with
> > 5lvl enabled.
> > 
> > Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>

Bah, and I thought I'm replying to v3. :-\

Anyway...

> What's your preference on timing? v6.17 or v6.16?

Right, here's what I'm thinking:

* Kirill's patches would simplify Ard's cleanup a bit

* The 4th one: Kirill A. Shutemov ( :  85|) ├─>[PATCHv3 4/4] x86/paravirt: Restrict PARAVIRT_XXL to 64-bit only

looks ok too.

So, I don't see anything speaking against queueing them *now* for the upcoming
merge window, I am testing the tip lineup on a daily basis this and next week
and if it all looks good, we could probably send them.

If not, we delay.

And if there's other issues which get detected later, during the 6.16-rc
phase, we revert.

So we have an exit route from each scenario.

So I guess let's...

Unless I'm missing an aspect.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCHv2 3/3] x86/64/mm: Make 5-level paging support unconditional

[Ingo Molnar]

* Borislav Petkov <bp@alien8.de> wrote:

> On Fri, May 16, 2025 at 05:46:51PM +0200, Ingo Molnar wrote:
> > 
> > * Borislav Petkov <bp@alien8.de> wrote:
> > 
> > > On Fri, May 16, 2025 at 12:15:33PM +0300, Kirill A. Shutemov wrote:
> > > > @@ -173,10 +173,10 @@ For example, when an old kernel is running on new hardware.
> > > >  The kernel disabled support for it at compile-time
> > > >  --------------------------------------------------
> > > >  
> > > > -For example, if 5-level-paging is not enabled when building (i.e.,
> > > > -CONFIG_X86_5LEVEL is not selected) the flag "la57" will not show up [#f1]_.
> > > > +For example, if Linear Address Masking (LAM) is not enabled when building (i.e.,
> > > > +CONFIG_ADDRESS_MASKING is not selected) the flag "lam" will not show up.
> > > >  Even though the feature will still be detected via CPUID, the kernel disables
> > > > -it by clearing via setup_clear_cpu_cap(X86_FEATURE_LA57).
> > > > +it by clearing via setup_clear_cpu_cap(X86_FEATURE_LAM).
> > > 
> > > LOL, good one.
> > > 
> > > The rest looks nice and good to me. And FWIW, it boots fine on my Zen5 with
> > > 5lvl enabled.
> > > 
> > > Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
> 
> Bah, and I thought I'm replying to v3. :-\
> 
> Anyway...
> 
> > What's your preference on timing? v6.17 or v6.16?
> 
> Right, here's what I'm thinking:
> 
> * Kirill's patches would simplify Ard's cleanup a bit

Yeah.

> * The 4th one: Kirill A. Shutemov ( :  85|) ├─>[PATCHv3 4/4] x86/paravirt: Restrict PARAVIRT_XXL to 64-bit only
> 
> looks ok too.

Yeah, and now has an Ack from Jürgen too.

> So, I don't see anything speaking against queueing them *now* for the 
> upcoming merge window, I am testing the tip lineup on a daily basis 
> this and next week and if it all looks good, we could probably send 
> them.

Cool!

> If not, we delay.
> 
> And if there's other issues which get detected later, during the 
> 6.16-rc phase, we revert.
> 
> So we have an exit route from each scenario.
> 
> So I guess let's...
> 
> Unless I'm missing an aspect.

I think that's a good plan. I've queued up Kirill's latest in 
tip:x86/core, with tags updated, and it boots fine on my
testsystems as well. Knock on wood. :)

Thanks,

	Ingo

Re: [PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

[Khalid Ali]

>Both Intel and AMD CPUs support 5-level paging, which is expected to
>become more widely adopted in the future.
>
>Remove CONFIG_X86_5LEVEL.
>
>In preparation to that remove CONFIG_DYNAMIC_MEMORY_LAYOUT and make
>SPARSEMEM_VMEMMAP the only memory model.
>
>v2:
> - Fix 32-bit build by wrapping p4d_set_huge() and p4d_clear_huge() in
>   #if CONFIG_PGTABLE_LEVELS > 4;
> - Rebased onto current tip/master;
>
>Kirill A. Shutemov (3):
>  x86/64/mm: Always use dynamic memory layout
>  x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model
>  x86/64/mm: Make 5-level paging support unconditional
>
> Documentation/arch/x86/cpuinfo.rst            |  8 ++---
> .../arch/x86/x86_64/5level-paging.rst         |  9 ------
> arch/x86/Kconfig                              | 32 ++-----------------
> arch/x86/Kconfig.cpufeatures                  |  4 ---
> arch/x86/boot/compressed/pgtable_64.c         | 11 ++-----
> arch/x86/boot/header.S                        |  4 ---
> arch/x86/boot/startup/map_kernel.c            |  5 +--
> arch/x86/include/asm/page_64.h                |  2 --
> arch/x86/include/asm/page_64_types.h          | 11 -------
> arch/x86/include/asm/pgtable_64_types.h       | 24 --------------
> arch/x86/kernel/alternative.c                 |  2 +-
> arch/x86/kernel/head64.c                      |  4 ---
> arch/x86/kernel/head_64.S                     |  2 --
> arch/x86/mm/init.c                            |  4 ---
> arch/x86/mm/init_64.c                         |  9 +-----
> arch/x86/mm/pgtable.c                         |  2 +-
> drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
> scripts/gdb/linux/pgtable.py                  |  4 +--
> 18 files changed, 13 insertions(+), 126 deletions(-)

I think i am too late, however this is completely wrong. There are still processors that doesn't support
5-level paging which is mordern. We may call those processors old, however they are still common and used.

So this patch seem too early for that. Some intel core-i5 and core-i7 doesn't support 5-level paging at all.

This will break x86_64 cpus that doesn't support 5-level paging.

Re: [PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

[H. Peter Anvin]

On June 24, 2025 1:11:15 AM PDT, Khalid Ali <khaliidcaliy@gmail.com> wrote:
>>Both Intel and AMD CPUs support 5-level paging, which is expected to
>>become more widely adopted in the future.
>>
>>Remove CONFIG_X86_5LEVEL.
>>
>>In preparation to that remove CONFIG_DYNAMIC_MEMORY_LAYOUT and make
>>SPARSEMEM_VMEMMAP the only memory model.
>>
>>v2:
>> - Fix 32-bit build by wrapping p4d_set_huge() and p4d_clear_huge() in
>>   #if CONFIG_PGTABLE_LEVELS > 4;
>> - Rebased onto current tip/master;
>>
>>Kirill A. Shutemov (3):
>>  x86/64/mm: Always use dynamic memory layout
>>  x86/64/mm: Make SPARSEMEM_VMEMMAP the only memory model
>>  x86/64/mm: Make 5-level paging support unconditional
>>
>> Documentation/arch/x86/cpuinfo.rst            |  8 ++---
>> .../arch/x86/x86_64/5level-paging.rst         |  9 ------
>> arch/x86/Kconfig                              | 32 ++-----------------
>> arch/x86/Kconfig.cpufeatures                  |  4 ---
>> arch/x86/boot/compressed/pgtable_64.c         | 11 ++-----
>> arch/x86/boot/header.S                        |  4 ---
>> arch/x86/boot/startup/map_kernel.c            |  5 +--
>> arch/x86/include/asm/page_64.h                |  2 --
>> arch/x86/include/asm/page_64_types.h          | 11 -------
>> arch/x86/include/asm/pgtable_64_types.h       | 24 --------------
>> arch/x86/kernel/alternative.c                 |  2 +-
>> arch/x86/kernel/head64.c                      |  4 ---
>> arch/x86/kernel/head_64.S                     |  2 --
>> arch/x86/mm/init.c                            |  4 ---
>> arch/x86/mm/init_64.c                         |  9 +-----
>> arch/x86/mm/pgtable.c                         |  2 +-
>> drivers/firmware/efi/libstub/x86-5lvl.c       |  2 +-
>> scripts/gdb/linux/pgtable.py                  |  4 +--
>> 18 files changed, 13 insertions(+), 126 deletions(-)
>
>I think i am too late, however this is completely wrong. There are still processors that doesn't support
>5-level paging which is mordern. We may call those processors old, however they are still common and used.
>
>So this patch seem too early for that. Some intel core-i5 and core-i7 doesn't support 5-level paging at all.
>
>This will break x86_64 cpus that doesn't support 5-level paging.

Uh, no. Kernels compiled with 5-level support also support 4 levels.

Re: [PATCHv2 0/3] x86: Make 5-level paging support unconditional for x86-64

[Kirill A. Shutemov]

On Tue, Jun 24, 2025 at 08:11:15AM +0000, Khalid Ali wrote:
> This will break x86_64 cpus that doesn't support 5-level paging.

No, it won't.

The patchset removes compile-time config option to disable 5-level paging.
After tha patchset all kernels will be built with 5-level paging *support*.

The actual paging mode is chosen at boot time based on machine
capabilities and kernel command line. Older HW will boot in 4-level paging
mode just fine.

-- 
  Kiryl Shutsemau / Kirill A. Shutemov