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charset=UTF-8 Date: Thu, 19 Mar 2026 11:07:04 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Miguel Ojeda" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Trevor Gross" , "John Hubbard" , "Alistair Popple" , "Joel Fernandes" , "Timur Tabi" , "Zhi Wang" , , , , , Subject: Re: [PATCH 1/8] gpu: nova-core: convert PMC registers to kernel register macro From: "Alexandre Courbot" To: "Eliot Courtney" References: <20260318-b4-nova-register-v1-0-22a358aa4c63@nvidia.com> <20260318-b4-nova-register-v1-1-22a358aa4c63@nvidia.com> In-Reply-To: X-ClientProxiedBy: OS3P286CA0043.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:1f5::11) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|PH7PR12MB6585:EE_ X-MS-Office365-Filtering-Correlation-Id: 481c8ecc-2867-4bea-758a-08de855c394e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|1800799024|376014|7416014|22082099003|56012099003|18002099003; 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It should, thanks. > >> prelude::*, >> sync::aref::ARef, >> time::Delta, >> @@ -532,7 +535,7 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result { >> self.hal.reset_wait_mem_scrubbing(bar)?; >> =20 >> regs::NV_PFALCON_FALCON_RM::default() >> - .set_value(regs::NV_PMC_BOOT_0::read(bar).into()) >> + .set_value(bar.read(regs::NV_PMC_BOOT_0).into()) >> .write(bar, &E::ID); >> =20 >> Ok(()) >> diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs >> index 8579d632e717..d81abc7de3d7 100644 >> --- a/drivers/gpu/nova-core/gpu.rs >> +++ b/drivers/gpu/nova-core/gpu.rs >> @@ -4,6 +4,8 @@ >> device, >> devres::Devres, >> fmt, >> + io::Io, >> + num::Bounded, >> pci, >> prelude::*, >> sync::Arc, // >> @@ -129,24 +131,18 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::= Result { >> } >> =20 >> /// Enum representation of the GPU generation. >> -/// >> -/// TODO: remove the `Default` trait implementation, and the `#[default= ]` >> -/// attribute, once the register!() macro (which creates Architecture i= tems) no >> -/// longer requires it for read-only fields. >> -#[derive(fmt::Debug, Default, Copy, Clone)] >> -#[repr(u8)] >> +#[derive(fmt::Debug, Copy, Clone)] >> pub(crate) enum Architecture { >> - #[default] >> Turing =3D 0x16, >> Ampere =3D 0x17, >> Ada =3D 0x19, >> } >> =20 >> -impl TryFrom for Architecture { >> +impl TryFrom> for Architecture { >> type Error =3D Error; >> =20 >> - fn try_from(value: u8) -> Result { >> - match value { >> + fn try_from(value: Bounded) -> Result { >> + match u8::from(value) { >> 0x16 =3D> Ok(Self::Turing), >> 0x17 =3D> Ok(Self::Ampere), >> 0x19 =3D> Ok(Self::Ada), >> @@ -155,23 +151,26 @@ fn try_from(value: u8) -> Result { >> } >> } >> =20 >> -impl From for u8 { >> +impl From for Bounded { >> fn from(value: Architecture) -> Self { >> - // CAST: `Architecture` is `repr(u8)`, so this cast is always l= ossless. >> - value as u8 >> + match value { >> + Architecture::Turing =3D> Bounded::::new::<0x16>(), >> + Architecture::Ampere =3D> Bounded::::new::<0x17>(), >> + Architecture::Ada =3D> Bounded::::new::<0x19>(), >> + } >> } >> } >> =20 >> pub(crate) struct Revision { >> - major: u8, >> - minor: u8, >> + major: Bounded, >> + minor: Bounded, >> } >> =20 >> impl From for Revision { >> fn from(boot0: regs::NV_PMC_BOOT_42) -> Self { >> Self { >> - major: boot0.major_revision(), >> - minor: boot0.minor_revision(), >> + major: boot0.major_revision().cast(), >> + minor: boot0.minor_revision().cast(), >> } >> } >> } >> @@ -208,13 +207,13 @@ fn new(dev: &device::Device, bar: &Bar0) -> Result= { >> // from an earlier (pre-Fermi) era, and then using boot42 t= o precisely identify the GPU. >> // Somewhere in the Rubin timeframe, boot0 will no longer h= ave space to add new GPU IDs. >> =20 >> - let boot0 =3D regs::NV_PMC_BOOT_0::read(bar); >> + let boot0 =3D bar.read(regs::NV_PMC_BOOT_0); >> =20 >> if boot0.is_older_than_fermi() { >> return Err(ENODEV); >> } >> =20 >> - let boot42 =3D regs::NV_PMC_BOOT_42::read(bar); >> + let boot42 =3D bar.read(regs::NV_PMC_BOOT_42); >> Spec::try_from(boot42).inspect_err(|_| { >> dev_err!(dev, "Unsupported chipset: {}\n", boot42); >> }) >> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.= rs >> index 53f412f0ca32..62c2065e63ef 100644 >> --- a/drivers/gpu/nova-core/regs.rs >> +++ b/drivers/gpu/nova-core/regs.rs >> @@ -35,20 +35,64 @@ >> num::FromSafeCast, >> }; >> =20 >> +// All nova-core registers are 32-bit and `pub(crate)`. Wrap the `regis= ter!` macro to avoid >> +// repeating this information for every register. >> +macro_rules! nv_reg { >> + ( >> + $( >> + $(#[$attr:meta])* $name:ident $([ $size:expr $(, stride =3D= $stride:expr)? ])? >> + $(@ $offset:literal)? >> + $(@ $base:ident + $base_offset:literal)? >> + $(=3D> $alias:ident $(+ $alias_offset:ident)? $([$alias= _idx:expr])? )? >> + $(, $comment:literal)? { $($fields:tt)* } >> + )* >> + )=3D> { >> + $( >> + ::kernel::io::register!( >> + @reg $(#[$attr])* pub(crate) $name(u32) $([$size $(, stride= =3D $stride)?])? >> + $(@ $offset)? >> + $(@ $base + $base_offset)? >> + $(=3D> $alias $(+ $alias_offset)? $([$alias_idx])? )? >> + $(, $comment)? { $($fields)* } >> + ); >> + )* >> + }; >> +} >> + > > Is it really worth introducing this macro to save pub(crate) and (u32)? > Are we definitely going to always be using pub(crate) and u32? So far we are. I'm not particularly passionate about it, but I think it's nice not having to repeat ourselves (and potentially introduce typos).