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charset=UTF-8 Date: Sat, 21 Mar 2026 15:19:24 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Miguel Ojeda" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Trevor Gross" , "John Hubbard" , "Alistair Popple" , "Timur Tabi" , "Zhi Wang" , "Eliot Courtney" , , , , , Subject: Re: [PATCH v2 06/10] gpu: nova-core: convert PDISP registers to kernel register macro From: "Alexandre Courbot" To: "Joel Fernandes" References: <20260320-b4-nova-register-v2-0-88fcf103e8d4@nvidia.com> <20260320-b4-nova-register-v2-6-88fcf103e8d4@nvidia.com> <0231b5bc-03f0-4207-b0c4-fb6daf19d135@nvidia.com> In-Reply-To: <0231b5bc-03f0-4207-b0c4-fb6daf19d135@nvidia.com> X-ClientProxiedBy: TYCP286CA0175.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c6::14) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|CYXPR12MB9339:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c970985-7c29-49b3-49b0-08de8711ce1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|366016|10070799003|56012099003|22082099003|18002099003; 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>> =20 >> if hal.supports_display(bar) { >> - match regs::NV_PDISP_VGA_WORKSPACE_BASE::read(bar).= vga_workspace_addr() { >> + match bar >> + .read(regs::NV_PDISP_VGA_WORKSPACE_BASE) >> + .vga_workspace_addr() >> + { >> Some(addr) =3D> { >> if addr < base { >> const VBIOS_WORKSPACE_SIZE: u64 =3D usi= ze_as_u64(SZ_128K); >> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.= rs >> index 61a8dba22d88..b051d5568cd8 100644 >> --- a/drivers/gpu/nova-core/regs.rs >> +++ b/drivers/gpu/nova-core/regs.rs >> @@ -250,10 +250,14 @@ pub(crate) fn usable_fb_size(self) -> u64 { >> =20 >> // PDISP >> =20 >> -register!(NV_PDISP_VGA_WORKSPACE_BASE @ 0x00625f04 { >> - 3:3 status_valid as bool, "Set if the `addr` field is valid"; >> - 31:8 addr as u32, "VGA workspace base address divided by 0x10000= "; >> -}); >> +io::register! { >> + pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { >> + /// VGA workspace base address divided by 0x10000. >> + 31:8 addr; >> + /// Set if the `addr` field is valid. >> + 3:3 status_valid =3D> bool; >> + } >> +} > > Shouldn't this re-ordering of bit ranges be a separate patch? Also, what = did we > conclude on the ordering issue? I remember this was discussed, but I am n= ot sure > what the conclusion was. The conclusion was descending order for both bitfields and the bits themselves. This is part of the contract for using the `register!` macro, so I don't think it is out of place in this series (and re-shuffling things again won't make this diff smaller or more readable, so I don't think there is a benefit).