From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: matthew.gerlach@linux.intel.com
Cc: Bagas Sanjaya <bagasdotme@gmail.com>,
hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
niklas.soderlund+renesas@ragnatech.se, macro@orcam.me.uk,
johan@kernel.org, lukas@wunner.de, ilpo.jarvinen@linux.intel.com,
marpagan@redhat.com
Subject: Re: [PATCH v6 1/4] Documentation: fpga: dfl: Add documentation for DFHv1
Date: Tue, 13 Dec 2022 21:52:29 +0200 [thread overview]
Message-ID: <Y5jX/eXrFdAO7xml@smile.fi.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.22.394.2212130844330.3732069@rhweight-WRK1>
On Tue, Dec 13, 2022 at 08:50:25AM -0800, matthew.gerlach@linux.intel.com wrote:
> On Sat, 10 Dec 2022, Bagas Sanjaya wrote:
> > On Fri, Dec 09, 2022 at 01:45:20PM -0800, matthew.gerlach@linux.intel.com wrote:
...
> > > Open discussion
> > > ===============
> > > FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
> >
> > What about this wording below (including fitting the prose within 80 columns)?
>
> The wording you suggest is an improvement. I will include your suggestions.
> I mistakenly thought that Restructured Text needed list items to be a single
> line and checkpatch.pl did not flag the long lines.
I usually test the output with rst2pdf. You can also try kernel doc script to
produce man and HTML and see how they are rendered.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-12-13 19:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-09 21:45 [PATCH v6 0/4] Enhance definition of DFH and use enhancements for UART driver matthew.gerlach
2022-12-09 21:45 ` [PATCH v6 1/4] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-12-10 3:17 ` Bagas Sanjaya
2022-12-13 16:50 ` matthew.gerlach
2022-12-13 19:52 ` Andy Shevchenko [this message]
2022-12-13 20:41 ` matthew.gerlach
2022-12-09 21:45 ` [PATCH v6 2/4] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-12-09 21:45 ` [PATCH v6 3/4] fpga: dfl: add basic support for DFHv1 matthew.gerlach
2022-12-13 5:26 ` Xu Yilun
2022-12-09 21:45 ` [PATCH v6 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
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