From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
Will Deacon <will@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki Poulose <suzuki.poulose@arm.com>,
coresight@lists.linaro.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 1/7] arm64: Add Cortex-A510 CPU part definition
Date: Fri, 7 Jan 2022 10:56:58 +0000 [thread overview]
Message-ID: <YdgcegdfpV6eCvXl@arm.com> (raw)
In-Reply-To: <1641517808-5735-2-git-send-email-anshuman.khandual@arm.com>
On Fri, Jan 07, 2022 at 06:40:02AM +0530, Anshuman Khandual wrote:
> Add the CPU Partnumbers for the new Arm designs.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
next prev parent reply other threads:[~2022-01-07 10:57 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 1:10 [PATCH V2 0/7] coresight: trbe: Workaround Cortex-A510 erratas Anshuman Khandual
2022-01-07 1:10 ` [PATCH V2 1/7] arm64: Add Cortex-A510 CPU part definition Anshuman Khandual
2022-01-07 10:56 ` Catalin Marinas [this message]
2022-01-07 1:10 ` [PATCH V2 2/7] arm64: errata: Add detection for TRBE ignored system register writes Anshuman Khandual
2022-01-07 10:58 ` Catalin Marinas
2022-01-07 11:39 ` Suzuki K Poulose
2022-01-07 1:10 ` [PATCH V2 3/7] arm64: errata: Add detection for TRBE invalid prohibited states Anshuman Khandual
2022-01-07 10:59 ` Catalin Marinas
2022-01-07 11:56 ` Suzuki K Poulose
2022-01-07 1:10 ` [PATCH V2 4/7] arm64: errata: Add detection for TRBE trace data corruption Anshuman Khandual
2022-01-07 10:59 ` Catalin Marinas
2022-01-07 11:58 ` Suzuki K Poulose
2022-01-07 1:10 ` [PATCH V2 5/7] coresight: trbe: Work around the ignored system register writes Anshuman Khandual
2022-01-10 11:03 ` Suzuki K Poulose
2022-01-10 11:59 ` Anshuman Khandual
2022-01-07 1:10 ` [PATCH V2 6/7] coresight: trbe: Work around the invalid prohibited states Anshuman Khandual
2022-01-10 12:03 ` Suzuki K Poulose
2022-01-07 1:10 ` [PATCH V2 7/7] coresight: trbe: Work around the trace data corruption Anshuman Khandual
2022-01-10 12:04 ` Suzuki K Poulose
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YdgcegdfpV6eCvXl@arm.com \
--to=catalin.marinas@arm.com \
--cc=anshuman.khandual@arm.com \
--cc=coresight@lists.linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mathieu.poirier@linaro.org \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).