From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D85CBC00140 for ; Fri, 5 Aug 2022 09:08:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240259AbiHEJIP (ORCPT ); Fri, 5 Aug 2022 05:08:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235839AbiHEJIO (ORCPT ); Fri, 5 Aug 2022 05:08:14 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BC9F21E10; Fri, 5 Aug 2022 02:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659690493; x=1691226493; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=VCbk/q9Wd0lGTGIEGbC69VxKX0QDmTy8SvpJ1KoCfF0=; b=biSEyLDpCGbC085vqq4/C7VcR++Gz//BsrGNyI6UYr4FpmOL3E1o6lR2 TikNhO5QuSbvVNEFVIt3KNTiCwKRxvcBluqyClmMyYPHpmwrRFoX/RW+V LHG6mD4MDTWoUi+QO5WBxylKaYOYMmZ6VrZjCKzU2tZzrHq9ZKFgZWTuD obUhfGUVuGRwjMrTy5OsaY4LS/Tw66zzFebJOax3Qcx9rAylKisq2lMIt zdnjoxFDc3BGrF+hES5qwMEnAbaVJQw0HJYF20W9ldCk6senONYh1/dLk 9nECiHfPoOE/fadh/BNwz0PQbZ6uqc5+kg7o0xtvw/Sp9Nl5WXIJBIg1F Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="316045584" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="316045584" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 02:08:13 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="631945398" Received: from mborg-mobl1.ger.corp.intel.com (HELO intel.com) ([10.251.214.158]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2022 02:08:07 -0700 Date: Fri, 5 Aug 2022 11:08:05 +0200 From: Andi Shyti To: Randy Dunlap Cc: Mauro Carvalho Chehab , Jonathan Corbet , Niranjana Vishwanathapura , Andi Shyti , Tvrtko Ursulin , Chris Wilson , Daniel Vetter , David Airlie , Jani Nikula , Joonas Lahtinen , Maarten Lankhorst , Maxime Ripard , Rodrigo Vivi , Thomas Zimmermann , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions Message-ID: References: <0698c5a5-3bf2-daa4-e10e-2715f9b0d080@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0698c5a5-3bf2-daa4-e10e-2715f9b0d080@infradead.org> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org Hi Randy, > > +/** > > + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation > > + * @gt: GT structure > > In multiple places (here and below) it would be nice to know what a > GT structure is. I looked thru multiple C and header files yesterday > and didn't find any comments about it. > > Just saying that @gt is a GT structure isn't very helpful, other > than making kernel-doc shut up. the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and it's widely used a throughout i915. I think it's inappropriate to describe it just here. On the other hand I agree that a better documentation is required for the GT itself where other parts can point to. Andi