From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: matthew.gerlach@linux.intel.com
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v1 5/5] tty: serial: 8250: add DFL bus driver for Altera 16550.
Date: Mon, 12 Sep 2022 13:54:20 +0300 [thread overview]
Message-ID: <Yx8P3ABrwYaMBRhn@smile.fi.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.22.394.2209110850120.142336@rhweight-WRK1>
On Sun, Sep 11, 2022 at 08:56:41AM -0700, matthew.gerlach@linux.intel.com wrote:
> On Fri, 9 Sep 2022, Andy Shevchenko wrote:
> > On Thu, Sep 08, 2022 at 11:27:03AM -0700, matthew.gerlach@linux.intel.com wrote:
> > > On Tue, 6 Sep 2022, Andy Shevchenko wrote:
> > > > On Tue, Sep 06, 2022 at 12:04:26PM -0700, matthew.gerlach@linux.intel.com wrote:
...
> > > > > + dev_dbg(dfluart->dev, "UART_CLK_ID %llu Hz\n", dfluart->uart_clk);
> > > >
> > > > Isn't this available via normal interfaces to user?
> > >
> > > I am not sure what "normal interfaces to user" you are referring to. The
> > > code is just trying to read the frequency of the input clock to the uart
> > > from a DFH paramter.
> >
> > I mean dev_dbg() call. The user can get uart_clk via one of the UART/serial
> > ABIs (don't remember which one, though).
>
> I don't think UART/serial ABIs to get the input clock frequency would be
> available until after the call to serial8250_register_8250_port()
Is it a problem?
> which needs the clock frequency as an input.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-09-12 10:54 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 19:04 [PATCH v1 0/5] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 1/5] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-06 20:08 ` Andy Shevchenko
2022-09-07 19:15 ` matthew.gerlach
2022-09-11 9:57 ` Xu Yilun
2022-09-11 16:06 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 2/5] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-06 20:07 ` Andy Shevchenko
2022-09-07 21:01 ` matthew.gerlach
2022-09-07 5:08 ` Greg KH
2022-09-11 15:40 ` matthew.gerlach
2022-09-11 17:54 ` Geert Uytterhoeven
2022-09-11 8:04 ` Xu Yilun
2022-09-11 16:13 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-11 8:27 ` Xu Yilun
2022-09-11 16:21 ` matthew.gerlach
2022-09-06 19:04 ` [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-06 20:15 ` Andy Shevchenko
2022-09-07 21:37 ` matthew.gerlach
2022-09-08 11:04 ` Andy Shevchenko
2022-09-08 17:34 ` matthew.gerlach
2022-09-08 17:51 ` Andy Shevchenko
2022-09-08 19:28 ` Geert Uytterhoeven
2022-09-08 20:21 ` matthew.gerlach
2022-09-11 9:06 ` Xu Yilun
2022-09-06 19:04 ` [PATCH v1 5/5] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-06 20:24 ` Andy Shevchenko
2022-09-08 18:27 ` matthew.gerlach
2022-09-08 21:16 ` Andy Shevchenko
2022-09-11 15:56 ` matthew.gerlach
2022-09-12 10:54 ` Andy Shevchenko [this message]
2022-09-11 9:41 ` Xu Yilun
2022-09-12 15:29 ` matthew.gerlach
2022-09-13 2:48 ` Xu Yilun
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