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Tue, 25 Mar 2025 18:53:45 -0700 (PDT) Received: by archie.me (Postfix, from userid 1000) id AD0C54230C05; Wed, 26 Mar 2025 08:53:43 +0700 (WIB) Date: Wed, 26 Mar 2025 08:53:43 +0700 From: Bagas Sanjaya To: Rodrigo Siqueira , Alex Deucher , 'Christian =?utf-8?Q?K=C3=B6nig'?= , Mario Limonciello , Melissa Wen , =?utf-8?Q?'Andr=C3=A9?= Almeida' , 'Timur =?utf-8?B?S3Jpc3TDs2Yn?= Cc: amd-gfx@lists.freedesktop.org, linux-doc@vger.kernel.org, kernel-dev@igalia.com Subject: Re: [PATCH 4/6] Documentation/gpu: Add explanation about AMD Pipes and Queues Message-ID: References: <20250325172623.225901-1-siqueira@igalia.com> <20250325172623.225901-5-siqueira@igalia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="/mnH3a2A936fTjj8" Content-Disposition: inline In-Reply-To: <20250325172623.225901-5-siqueira@igalia.com> --/mnH3a2A936fTjj8 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 25, 2025 at 11:18:45AM -0600, Rodrigo Siqueira wrote: > +.. kernel-figure:: pipe_and_queue_abstraction.svg > + > +In the central part of this figure, you can see two elements, one called Did you mean hardware block? > +**Pipe** and another named **Queues**; it is important to highlight that= Queues > +must be associated with a Pipe and vice-versa. Every specific hardware m= ay have > +a different number of Pipes and, in turn, a different number of Queues; = for > +example, GFX 11 has two Pipes and two Queues=C2=A0per Pipe. > + > +Pipe is the hardware that processes the instructions available in the Qu= eues; > +in other words, it is a thread executing the operations inserted in the = Queue. > +One crucial characteristic of Pipes is that they can only execute one Qu= eue at > +a time; no matter if the hardware has multiple Queues in the Pipe, it on= ly runs > +one Queue per Pipe. When a queue is running in the Pipe, it is said that= the > +Queue is **Active**. > + > +Pipes have the mechanics of swapping between queues at the hardware leve= l. > +Nonetheless, they only make use of Queues that are considered mapped. Pi= pes can > +switch between queues based on any of the following inputs: > + > +1. Command Stream; > +2. Packet by Packet; > +3. Other hardware requests the change (e.g., MES). > + > +Queues within Pipes are defined by the Hardware Queue Descriptors (HQD). > +Associated with the HQD concept, we have the Memory Queue Descriptor (MQ= D), Related to HQD, we have MQD? > +which is responsible for storing information about the state of each of = the > +available Queues in the memory. The state of a Queue contains informatio= n such > +as the GPU virtual address of the queue itself, save areas, doorbell, et= c. The > +MQD also stores the HQD registers, which are vital for activating or > +deactivating a given Queue. > + Thanks. --=20 An old man doll... just what I always wanted! - Clara --/mnH3a2A936fTjj8 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQSSYQ6Cy7oyFNCHrUH2uYlJVVFOowUCZ+NeGQAKCRD2uYlJVVFO oye9AP4iR8Vfseiyzk8xEC38+vn4Jm0SA+1phHuaBIUg4JgxTAEA0b0qh5O2KT7G AqtO7nxuNxNoBeaZD1kAxX4AszF8DQA= =TdVl -----END PGP SIGNATURE----- --/mnH3a2A936fTjj8--