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Tue, 25 Mar 2025 18:58:24 -0700 (PDT) Received: by archie.me (Postfix, from userid 1000) id A04E54230C05; Wed, 26 Mar 2025 08:58:21 +0700 (WIB) Date: Wed, 26 Mar 2025 08:58:21 +0700 From: Bagas Sanjaya To: Rodrigo Siqueira , Alex Deucher , 'Christian =?utf-8?Q?K=C3=B6nig'?= , Mario Limonciello , Melissa Wen , =?utf-8?Q?'Andr=C3=A9?= Almeida' , 'Timur =?utf-8?B?S3Jpc3TDs2Yn?= Cc: amd-gfx@lists.freedesktop.org, linux-doc@vger.kernel.org, kernel-dev@igalia.com Subject: Re: [PATCH 6/6] Documentation/gpu: Add an intro about MES Message-ID: References: <20250325172623.225901-1-siqueira@igalia.com> <20250325172623.225901-7-siqueira@igalia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="T7r84Huw4Mg6PNRy" Content-Disposition: inline In-Reply-To: <20250325172623.225901-7-siqueira@igalia.com> --T7r84Huw4Mg6PNRy Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 25, 2025 at 11:18:47AM -0600, Rodrigo Siqueira wrote: > diff --git a/Documentation/gpu/amdgpu/gc/mes.rst b/Documentation/gpu/amdg= pu/gc/mes.rst > new file mode 100644 > index 000000000000..b99eb211b179 > --- /dev/null > +++ b/Documentation/gpu/amdgpu/gc/mes.rst > @@ -0,0 +1,38 @@ > +.. _amdgpu-mes: > + > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D > + MicroEngine Scheduler (MES) > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D > + > +.. note:: > + Queue and ring buffer are used as a synonymous. > + > +.. note:: > + This section assumes that you are familiar with the concept of Pipes,= Queues, and GC. > + If not, check :ref:`GFX, Compute, and SDMA Overall Behavior` > + and :ref:`drm/amdgpu - Graphics and Compute (GC) `. > + > +Every GFX has a pipe component with one or more hardware queues. Pipes c= an > +switch between queues depending on certain conditions, and one of the > +components that can request a queue switch to a pipe is the MicroEngine > +Scheduler (MES). Whenever the driver is initialized, it creates one MQD = per > +hardware queue, and then the MQDs are handed to the MES firmware for map= ping > +to: > + > +1. Kernel Queues (legacy): This queue is statically mapped to HQDs and n= ever > + preempted. Even though this is a legacy feature, it is the current de= fault, and > + most existing hardware supports it. When an application submits work = to the > + kernel driver, it submits all of the application command buffers to t= he kernel > + queues. The CS IOCTL takes the command buffer from the applications a= nd > + schedules them on the kernel queue. > + > +2. User Queues: These queues are dynamically mapped to the HQDs. Regardi= ng the > + utilization of User Queues, the userspace application will create its= user > + queues and submit work directly to its user queues with no need to IO= CTL for > + each submission and no need to share a single kernel queue. > + > +In terms of User Queues, MES can dynamically map them to the HQD. If the= re are > +more MQDs than HQDs, the MES firmware will preempt other user queues to = make > +sure each queues get a time slice; in other words, MES is a microcontrol= ler > +that handles the mapping and unmapping of MQDs into HQDs, as well as the > +priorities and oversubscription of MQDs. The doc LGTM, thanks! Reviewed-by: Bagas Sanjaya --=20 An old man doll... just what I always wanted! - Clara --T7r84Huw4Mg6PNRy Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQSSYQ6Cy7oyFNCHrUH2uYlJVVFOowUCZ+NfPQAKCRD2uYlJVVFO o6UAAP9lsXJ6l4cqF7vmeIBW9n4YJ2zC41NH/uOp6yO5dvxAzgD/WuufE/4Enb/F 3EDZtK7z4NvrYU2wMCsKX+SSFoHxUAs= =xTf7 -----END PGP SIGNATURE----- --T7r84Huw4Mg6PNRy--