[PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Anshuman Khandual]

This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
being used in the kernel. This is required to prevent their EL1 access trap
into EL2.

PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
for now as it does not get accessed in the kernel, and there is no plan for
its access from user space.

I have taken the liberty to pick up all the review tags for patches related
to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.

https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/

Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
FEAT_PMUv3p9 registers that are currently being used in kernel. The context
can be found here.

https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/

This series is based on v6.13-rc3

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mark Brown <robh@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Eric Auger <eric.auger@redhat.com>
Cc: kvmarm@lists.linux.dev
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org

Anshuman Khandual (7):
  arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
  arm64/sysreg: Add register fields for HDFGRTR2_EL2
  arm64/sysreg: Add register fields for HDFGWTR2_EL2
  arm64/sysreg: Add register fields for HFGITR2_EL2
  arm64/sysreg: Add register fields for HFGRTR2_EL2
  arm64/sysreg: Add register fields for HFGWTR2_EL2
  arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

 Documentation/arch/arm64/booting.rst |  18 +++++
 arch/arm64/include/asm/el2_setup.h   |  25 +++++++
 arch/arm64/tools/sysreg              | 103 +++++++++++++++++++++++++++
 3 files changed, 146 insertions(+)

-- 
2.25.1

[PATCH 1/7] arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1

[Anshuman Khandual]

This updates ID_AA64MMFR0_EL1 register fields as per the definitions based
on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b081b54d6d22..a6cbe0dcd63b 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1591,6 +1591,7 @@ EndEnum
 UnsignedEnum	59:56	FGT
 	0b0000	NI
 	0b0001	IMP
+	0b0010	FGT2
 EndEnum
 Res0	55:48
 UnsignedEnum	47:44	EXS
@@ -1652,6 +1653,7 @@ Enum	3:0	PARANGE
 	0b0100	44
 	0b0101	48
 	0b0110	52
+	0b0111	56
 EndEnum
 EndSysreg
 
-- 
2.25.1

[PATCH 2/7] arm64/sysreg: Add register fields for HDFGRTR2_EL2

[Anshuman Khandual]

This adds register fields for HDFGRTR2_EL2 as per the definitions based
on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a6cbe0dcd63b..9ce8602dd40f 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2546,6 +2546,35 @@ Field	1	ICIALLU
 Field	0	ICIALLUIS
 EndSysreg
 
+Sysreg HDFGRTR2_EL2	3	4	3	1	0
+Res0	63:25
+Field	24	nPMBMAR_EL1
+Field	23	nMDSTEPOP_EL1
+Field	22	nTRBMPAM_EL1
+Res0	21
+Field	20	nTRCITECR_EL1
+Field	19	nPMSDSFR_EL1
+Field	18	nSPMDEVAFF_EL1
+Field	17	nSPMID
+Field	16	nSPMSCR_EL1
+Field	15	nSPMACCESSR_EL1
+Field	14	nSPMCR_EL0
+Field	13	nSPMOVS
+Field	12	nSPMINTEN
+Field	11	nSPMCNTEN
+Field	10	nSPMSELR_EL0
+Field	9	nSPMEVTYPERn_EL0
+Field	8	nSPMEVCNTRn_EL0
+Field	7	nPMSSCR_EL1
+Field	6	nPMSSDATA
+Field	5	nMDSELR_EL1
+Field	4	nPMUACR_EL1
+Field	3	nPMICFILTR_EL0
+Field	2	nPMICNTR_EL0
+Field	1	nPMIAR_EL1
+Field	0	nPMECR_EL1
+EndSysreg
+
 Sysreg HDFGRTR_EL2	3	4	3	1	4
 Field	63	PMBIDR_EL1
 Field	62	nPMSNEVFR_EL1
-- 
2.25.1

[PATCH 3/7] arm64/sysreg: Add register fields for HDFGWTR2_EL2

[Anshuman Khandual]

This adds register fields for HDFGWTR2_EL2 as per the definitions based
on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 9ce8602dd40f..f5a1fa75ec72 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2575,6 +2575,34 @@ Field	1	nPMIAR_EL1
 Field	0	nPMECR_EL1
 EndSysreg
 
+Sysreg HDFGWTR2_EL2	3	4	3	1	1
+Res0	63:25
+Field	24	nPMBMAR_EL1
+Field	23	nMDSTEPOP_EL1
+Field	22	nTRBMPAM_EL1
+Field	21	nPMZR_EL0
+Field	20	nTRCITECR_EL1
+Field	19	nPMSDSFR_EL1
+Res0	18:17
+Field	16	nSPMSCR_EL1
+Field	15	nSPMACCESSR_EL1
+Field	14	nSPMCR_EL0
+Field	13	nSPMOVS
+Field	12	nSPMINTEN
+Field	11	nSPMCNTEN
+Field	10	nSPMSELR_EL0
+Field	9	nSPMEVTYPERn_EL0
+Field	8	nSPMEVCNTRn_EL0
+Field	7	nPMSSCR_EL1
+Res0	6
+Field	5	nMDSELR_EL1
+Field	4	nPMUACR_EL1
+Field	3	nPMICFILTR_EL0
+Field	2	nPMICNTR_EL0
+Field	1	nPMIAR_EL1
+Field	0	nPMECR_EL1
+EndSysreg
+
 Sysreg HDFGRTR_EL2	3	4	3	1	4
 Field	63	PMBIDR_EL1
 Field	62	nPMSNEVFR_EL1
-- 
2.25.1

[PATCH 4/7] arm64/sysreg: Add register fields for HFGITR2_EL2

[Anshuman Khandual]

This adds register fields for HFGITR2_EL2 as per the definitions based
on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index f5a1fa75ec72..088e3be8f884 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2775,6 +2775,12 @@ Field	1	AMEVCNTR00_EL0
 Field	0	AMCNTEN0
 EndSysreg
 
+Sysreg	HFGITR2_EL2	3	4	3	1	7
+Res0	63:2
+Field	1	nDCCIVAPS
+Field	0	TSBCSYNC
+EndSysreg
+
 Sysreg	ZCR_EL2	3	4	1	2	0
 Fields	ZCR_ELx
 EndSysreg
-- 
2.25.1

[PATCH 5/7] arm64/sysreg: Add register fields for HFGRTR2_EL2

[Anshuman Khandual]

This adds register fields for HFGRTR2_EL2 as per the definitions based
on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 088e3be8f884..0875e0057706 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2603,6 +2603,25 @@ Field	1	nPMIAR_EL1
 Field	0	nPMECR_EL1
 EndSysreg
 
+Sysreg	HFGRTR2_EL2	3	4	3	1	2
+Res0	63:15
+Field	14	nACTLRALIAS_EL1
+Field	13	nACTLRMASK_EL1
+Field	12	nTCR2ALIAS_EL1
+Field	11	nTCRALIAS_EL1
+Field	10	nSCTLRALIAS2_EL1
+Field	9	nSCTLRALIAS_EL1
+Field	8	nCPACRALIAS_EL1
+Field	7	nTCR2MASK_EL1
+Field	6	nTCRMASK_EL1
+Field	5	nSCTLR2MASK_EL1
+Field	4	nSCTLRMASK_EL1
+Field	3	nCPACRMASK_EL1
+Field	2	nRCWSMASK_EL1
+Field	1	nERXGSR_EL1
+Field	0	nPFAR_EL1
+EndSysreg
+
 Sysreg HDFGRTR_EL2	3	4	3	1	4
 Field	63	PMBIDR_EL1
 Field	62	nPMSNEVFR_EL1
-- 
2.25.1

[PATCH 6/7] arm64/sysreg: Add register fields for HFGWTR2_EL2

[Anshuman Khandual]

This adds register fields for HFGWTR2_EL2 as per the definitions based
on DDI0601 2024-09.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/tools/sysreg | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 0875e0057706..268f1b808e3f 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2622,6 +2622,25 @@ Field	1	nERXGSR_EL1
 Field	0	nPFAR_EL1
 EndSysreg
 
+Sysreg	HFGWTR2_EL2	3	4	3	1	3
+Res0	63:15
+Field	14	nACTLRALIAS_EL1
+Field	13	nACTLRMASK_EL1
+Field	12	nTCR2ALIAS_EL1
+Field	11	nTCRALIAS_EL1
+Field	10	nSCTLRALIAS2_EL1
+Field	9	nSCTLRALIAS_EL1
+Field	8	nCPACRALIAS_EL1
+Field	7	nTCR2MASK_EL1
+Field	6	nTCRMASK_EL1
+Field	5	nSCTLR2MASK_EL1
+Field	4	nSCTLRMASK_EL1
+Field	3	nCPACRMASK_EL1
+Field	2	nRCWSMASK_EL1
+Res0	1
+Field	0	nPFAR_EL1
+EndSysreg
+
 Sysreg HDFGRTR_EL2	3	4	3	1	4
 Field	63	PMBIDR_EL1
 Field	62	nPMSNEVFR_EL1
-- 
2.25.1

[PATCH 7/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Anshuman Khandual]

FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1
access from EL1 requires appropriate EL2 fine grained trap configuration
via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2.
Otherwise such register accesses will result in traps into EL2.

Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine
grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the
bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into
PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers.

Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2
based registers to be accessible in EL2.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-doc@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: kvmarm@lists.linux.dev
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 Documentation/arch/arm64/booting.rst | 18 ++++++++++++++++++
 arch/arm64/include/asm/el2_setup.h   | 25 +++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index 3278fb4bf219..57ca46577084 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -288,6 +288,12 @@ Before jumping into the kernel, the following conditions must be met:
 
     - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
 
+  For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present:
+
+  - If EL3 is present and the kernel is entered at EL2:
+
+    - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
+
   For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
 
   - If EL3 is present and the kernel is entered at EL2:
@@ -382,6 +388,18 @@ Before jumping into the kernel, the following conditions must be met:
 
     - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
 
+  For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9):
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+    - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
+    - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
+    - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
+
+    - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
+    - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
+    - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
+
   For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
 
   - If the kernel is entered at EL1 and EL2 is present:
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 4ef52d7245bb..9e44c13711e5 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -233,6 +233,30 @@
 .Lskip_fgt_\@:
 .endm
 
+.macro __init_el2_fgt2
+	mrs	x1, id_aa64mmfr0_el1
+	ubfx	x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
+	cmp	x1, #ID_AA64MMFR0_EL1_FGT_FGT2
+	b.lt	.Lskip_fgt2_\@
+
+	mov	x0, xzr
+	mrs	x1, id_aa64dfr0_el1
+	ubfx	x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
+	cmp	x1, #ID_AA64DFR0_EL1_PMUVer_V3P9
+	b.lt	.Lskip_pmuv3p9_\@
+
+	orr	x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0
+	orr	x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0
+	orr	x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1
+.Lskip_pmuv3p9_\@:
+	msr_s   SYS_HDFGRTR2_EL2, x0
+	msr_s   SYS_HDFGWTR2_EL2, x0
+	msr_s   SYS_HFGRTR2_EL2, xzr
+	msr_s   SYS_HFGWTR2_EL2, xzr
+	msr_s   SYS_HFGITR2_EL2, xzr
+.Lskip_fgt2_\@:
+.endm
+
 .macro __init_el2_gcs
 	mrs_s	x1, SYS_ID_AA64PFR1_EL1
 	ubfx	x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4
@@ -283,6 +307,7 @@
 	__init_el2_nvhe_idregs
 	__init_el2_cptr
 	__init_el2_fgt
+	__init_el2_fgt2
         __init_el2_gcs
 .endm
 
-- 
2.25.1

Re: [PATCH 7/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Rob Herring]

On Fri, Dec 20, 2024 at 12:52:40PM +0530, Anshuman Khandual wrote:
> FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1
> access from EL1 requires appropriate EL2 fine grained trap configuration
> via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2.
> Otherwise such register accesses will result in traps into EL2.
> 
> Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine
> grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the
> bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into
> PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers.
> 
> Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2
> based registers to be accessible in EL2.
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-doc@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: kvmarm@lists.linux.dev
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  Documentation/arch/arm64/booting.rst | 18 ++++++++++++++++++
>  arch/arm64/include/asm/el2_setup.h   | 25 +++++++++++++++++++++++++
>  2 files changed, 43 insertions(+)

Tested-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Rob Herring]

On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> being used in the kernel. This is required to prevent their EL1 access trap
> into EL2.
> 
> PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> for now as it does not get accessed in the kernel, and there is no plan for
> its access from user space.
> 
> I have taken the liberty to pick up all the review tags for patches related
> to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> 
> https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> 
> Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> can be found here.
> 
> https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> 
> This series is based on v6.13-rc3
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Ryan Roberts <ryan.roberts@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Mark Brown <robh@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: Eric Auger <eric.auger@redhat.com>
> Cc: kvmarm@lists.linux.dev
> Cc: linux-doc@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> 
> Anshuman Khandual (7):
>   arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
>   arm64/sysreg: Add register fields for HDFGRTR2_EL2
>   arm64/sysreg: Add register fields for HDFGWTR2_EL2
>   arm64/sysreg: Add register fields for HFGITR2_EL2
>   arm64/sysreg: Add register fields for HFGRTR2_EL2
>   arm64/sysreg: Add register fields for HFGWTR2_EL2
>   arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

In case it is not clear, this series should be applied to 6.13 as the 2 
PMUv3p9 features already landed in 6.13 (per counter EL0 control) and 
6.12 (ICNTR). 

Rob

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Catalin Marinas]

On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > being used in the kernel. This is required to prevent their EL1 access trap
> > into EL2.
> > 
> > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > for now as it does not get accessed in the kernel, and there is no plan for
> > its access from user space.
> > 
> > I have taken the liberty to pick up all the review tags for patches related
> > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > 
> > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > 
> > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > can be found here.
> > 
> > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > 
> > This series is based on v6.13-rc3
> > 
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Marc Zyngier <maz@kernel.org>
> > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Mark Brown <robh@kernel.org>
> > Cc: Rob Herring <robh@kernel.org>
> > Cc: Oliver Upton <oliver.upton@linux.dev>
> > Cc: Jonathan Corbet <corbet@lwn.net>
> > Cc: Eric Auger <eric.auger@redhat.com>
> > Cc: kvmarm@lists.linux.dev
> > Cc: linux-doc@vger.kernel.org
> > Cc: linux-kernel@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org
> > 
> > Anshuman Khandual (7):
> >   arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> >   arm64/sysreg: Add register fields for HDFGRTR2_EL2
> >   arm64/sysreg: Add register fields for HDFGWTR2_EL2
> >   arm64/sysreg: Add register fields for HFGITR2_EL2
> >   arm64/sysreg: Add register fields for HFGRTR2_EL2
> >   arm64/sysreg: Add register fields for HFGWTR2_EL2
> >   arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> 
> In case it is not clear, this series should be applied to 6.13 as the 2 
> PMUv3p9 features already landed in 6.13 (per counter EL0 control) and 
> 6.12 (ICNTR). 

So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
counter")? It's pretty late in the cycle to take the series for 6.13.

But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
than traps it at EL2?

-- 
Catalin

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Marc Zyngier]

On Tue, 07 Jan 2025 12:13:40 +0000,
Catalin Marinas <catalin.marinas@arm.com> wrote:
> 
> On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > being used in the kernel. This is required to prevent their EL1 access trap
> > > into EL2.
> > > 
> > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > for now as it does not get accessed in the kernel, and there is no plan for
> > > its access from user space.
> > > 
> > > I have taken the liberty to pick up all the review tags for patches related
> > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > > 
> > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > > 
> > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > can be found here.
> > > 
> > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > > 
> > > This series is based on v6.13-rc3
> > > 
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: Mark Brown <robh@kernel.org>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > Cc: Eric Auger <eric.auger@redhat.com>
> > > Cc: kvmarm@lists.linux.dev
> > > Cc: linux-doc@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org
> > > 
> > > Anshuman Khandual (7):
> > >   arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > >   arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > >   arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > >   arm64/sysreg: Add register fields for HFGITR2_EL2
> > >   arm64/sysreg: Add register fields for HFGRTR2_EL2
> > >   arm64/sysreg: Add register fields for HFGWTR2_EL2
> > >   arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> > 
> > In case it is not clear, this series should be applied to 6.13 as the 2 
> > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and 
> > 6.12 (ICNTR). 
> 
> So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> counter")? It's pretty late in the cycle to take the series for 6.13.
> 
> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> than traps it at EL2?

We limit the PMU emulation to v3p8, so *hopefully* this doesn't trip
anything in KVM, even if we don't advertise support for these
features. This has been tested, right?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Rob Herring]

On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > being used in the kernel. This is required to prevent their EL1 access trap
> > > into EL2.
> > >
> > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > for now as it does not get accessed in the kernel, and there is no plan for
> > > its access from user space.
> > >
> > > I have taken the liberty to pick up all the review tags for patches related
> > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > >
> > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > >
> > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > can be found here.
> > >
> > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > >
> > > This series is based on v6.13-rc3
> > >
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Marc Zyngier <maz@kernel.org>
> > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: Mark Brown <robh@kernel.org>
> > > Cc: Rob Herring <robh@kernel.org>
> > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > Cc: Eric Auger <eric.auger@redhat.com>
> > > Cc: kvmarm@lists.linux.dev
> > > Cc: linux-doc@vger.kernel.org
> > > Cc: linux-kernel@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org
> > >
> > > Anshuman Khandual (7):
> > >   arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > >   arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > >   arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > >   arm64/sysreg: Add register fields for HFGITR2_EL2
> > >   arm64/sysreg: Add register fields for HFGRTR2_EL2
> > >   arm64/sysreg: Add register fields for HFGWTR2_EL2
> > >   arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> >
> > In case it is not clear, this series should be applied to 6.13 as the 2
> > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > 6.12 (ICNTR).
>
> So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> counter")? It's pretty late in the cycle to take the series for 6.13.

Ideally, yes. But given the state of h/w implementations, backporting
it later is probably fine if that is your preference.

> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> than traps it at EL2?

As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
accesses to these registers are trapped with or without this series.

Rob

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Marc Zyngier]

On Tue, 07 Jan 2025 22:13:47 +0000,
Rob Herring <robh@kernel.org> wrote:
> 
> On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> >
> > On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > > being used in the kernel. This is required to prevent their EL1 access trap
> > > > into EL2.
> > > >
> > > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > > for now as it does not get accessed in the kernel, and there is no plan for
> > > > its access from user space.
> > > >
> > > > I have taken the liberty to pick up all the review tags for patches related
> > > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > > >
> > > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > > >
> > > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > > can be found here.
> > > >
> > > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > > >
> > > > This series is based on v6.13-rc3
> > > >
> > > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > > Cc: Will Deacon <will@kernel.org>
> > > > Cc: Marc Zyngier <maz@kernel.org>
> > > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > > Cc: Mark Brown <robh@kernel.org>
> > > > Cc: Rob Herring <robh@kernel.org>
> > > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > > Cc: Eric Auger <eric.auger@redhat.com>
> > > > Cc: kvmarm@lists.linux.dev
> > > > Cc: linux-doc@vger.kernel.org
> > > > Cc: linux-kernel@vger.kernel.org
> > > > Cc: linux-arm-kernel@lists.infradead.org
> > > >
> > > > Anshuman Khandual (7):
> > > >   arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > > >   arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > > >   arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > > >   arm64/sysreg: Add register fields for HFGITR2_EL2
> > > >   arm64/sysreg: Add register fields for HFGRTR2_EL2
> > > >   arm64/sysreg: Add register fields for HFGWTR2_EL2
> > > >   arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> > >
> > > In case it is not clear, this series should be applied to 6.13 as the 2
> > > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > > 6.12 (ICNTR).
> >
> > So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> > d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> > counter")? It's pretty late in the cycle to take the series for 6.13.
> 
> Ideally, yes. But given the state of h/w implementations, backporting
> it later is probably fine if that is your preference.
> 
> > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> > than traps it at EL2?
> 
> As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> accesses to these registers are trapped with or without this series.

And most probably generates a nice splat in the kernel log, as nobody
updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
with the FGT2 registers.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Rob Herring]

On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Tue, 07 Jan 2025 22:13:47 +0000,
> Rob Herring <robh@kernel.org> wrote:
> >
> > On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > >
> > > On Thu, Jan 02, 2025 at 10:04:02AM -0600, Rob Herring wrote:
> > > > On Fri, Dec 20, 2024 at 12:52:33PM +0530, Anshuman Khandual wrote:
> > > > > This series adds fine grained trap control in EL2 required for FEAT_PMUv3p9
> > > > > registers like PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 which are already
> > > > > being used in the kernel. This is required to prevent their EL1 access trap
> > > > > into EL2.
> > > > >
> > > > > PMZR_EL0 register trap control i.e HDFGWTR2_EL2.nPMZR_EL0 remains unchanged
> > > > > for now as it does not get accessed in the kernel, and there is no plan for
> > > > > its access from user space.
> > > > >
> > > > > I have taken the liberty to pick up all the review tags for patches related
> > > > > to tools sysreg update from the KVM FGT2 V2 patch series posted earlier.
> > > > >
> > > > > https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> > > > >
> > > > > Rob had earler mentioned about FEAT_FGT2 based trap control requirement for
> > > > > FEAT_PMUv3p9 registers that are currently being used in kernel. The context
> > > > > can be found here.
> > > > >
> > > > > https://lore.kernel.org/all/20241216234251.GA629562-robh@kernel.org/
> > > > >
> > > > > This series is based on v6.13-rc3
> > > > >
> > > > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > > > Cc: Will Deacon <will@kernel.org>
> > > > > Cc: Marc Zyngier <maz@kernel.org>
> > > > > Cc: Ryan Roberts <ryan.roberts@arm.com>
> > > > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > > > Cc: Mark Brown <robh@kernel.org>
> > > > > Cc: Rob Herring <robh@kernel.org>
> > > > > Cc: Oliver Upton <oliver.upton@linux.dev>
> > > > > Cc: Jonathan Corbet <corbet@lwn.net>
> > > > > Cc: Eric Auger <eric.auger@redhat.com>
> > > > > Cc: kvmarm@lists.linux.dev
> > > > > Cc: linux-doc@vger.kernel.org
> > > > > Cc: linux-kernel@vger.kernel.org
> > > > > Cc: linux-arm-kernel@lists.infradead.org
> > > > >
> > > > > Anshuman Khandual (7):
> > > > >   arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1
> > > > >   arm64/sysreg: Add register fields for HDFGRTR2_EL2
> > > > >   arm64/sysreg: Add register fields for HDFGWTR2_EL2
> > > > >   arm64/sysreg: Add register fields for HFGITR2_EL2
> > > > >   arm64/sysreg: Add register fields for HFGRTR2_EL2
> > > > >   arm64/sysreg: Add register fields for HFGWTR2_EL2
> > > > >   arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
> > > >
> > > > In case it is not clear, this series should be applied to 6.13 as the 2
> > > > PMUv3p9 features already landed in 6.13 (per counter EL0 control) and
> > > > 6.12 (ICNTR).
> > >
> > > So is this a fix that needs backporting to 6.12 or 6.13, e.g. fix for
> > > d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction
> > > counter")? It's pretty late in the cycle to take the series for 6.13.
> >
> > Ideally, yes. But given the state of h/w implementations, backporting
> > it later is probably fine if that is your preference.
> >
> > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> > > than traps it at EL2?
> >
> > As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> > accesses to these registers are trapped with or without this series.
>
> And most probably generates a nice splat in the kernel log, as nobody
> updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
> with the FGT2 registers.

Isn't that this series[1]? Should that have come first, I guess I know
that *now*.

Out of curiosity, why do we care if there's a splat or not for a not
well behaved guest?

Rob

[1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Marc Zyngier]

On Wed, 08 Jan 2025 13:47:16 +0000,
Rob Herring <robh@kernel.org> wrote:
>
> Out of curiosity, why do we care if there's a splat or not for a not
> well behaved guest?

The only well behaved guest is the one that doesn't run.

Getting that splat is an indication of a *KVM* bug which fails to
correctly emulate the architecture (feature not advertised ->
instructions must silently UNDEF).

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Catalin Marinas]

On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote:
> On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote:
> > On Tue, 07 Jan 2025 22:13:47 +0000,
> > Rob Herring <robh@kernel.org> wrote:
> > > On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> > > > than traps it at EL2?
> > >
> > > As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> > > accesses to these registers are trapped with or without this series.
> >
> > And most probably generates a nice splat in the kernel log, as nobody
> > updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
> > with the FGT2 registers.
> 
> Isn't that this series[1]? Should that have come first, I guess I know
> that *now*.
[...]
> [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/

It's not any clearer to me. Does this series depend on the 46-patch one?
Or, if we had the other, is this no longer needed? Or none of these,
they are independent.

-- 
Catalin

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Rob Herring]

On Thu, Jan 16, 2025 at 9:32 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
>
> On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote:
> > On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote:
> > > On Tue, 07 Jan 2025 22:13:47 +0000,
> > > Rob Herring <robh@kernel.org> wrote:
> > > > On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> > > > > But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> > > > > than traps it at EL2?
> > > >
> > > > As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> > > > accesses to these registers are trapped with or without this series.
> > >
> > > And most probably generates a nice splat in the kernel log, as nobody
> > > updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
> > > with the FGT2 registers.
> >
> > Isn't that this series[1]? Should that have come first, I guess I know
> > that *now*.
> [...]
> > [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
>
> It's not any clearer to me. Does this series depend on the 46-patch one?
> Or, if we had the other, is this no longer needed? Or none of these,
> they are independent.

They are independent. I think ideally we'd want everything landing at
the same time, but we're past ideal at this point. Without this
series, if someone uses PMU on v8.9 and firmware enabled FGT2, then
the kernel will crash. Without the above series, KVM will have
warnings in the kernel log, but otherwise function.

Rob

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Anshuman Khandual]

On 1/18/25 03:37, Rob Herring wrote:
> On Thu, Jan 16, 2025 at 9:32 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
>>
>> On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote:
>>> On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote:
>>>> On Tue, 07 Jan 2025 22:13:47 +0000,
>>>> Rob Herring <robh@kernel.org> wrote:
>>>>> On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
>>>>>> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
>>>>>> than traps it at EL2?
>>>>>
>>>>> As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
>>>>> accesses to these registers are trapped with or without this series.
>>>>
>>>> And most probably generates a nice splat in the kernel log, as nobody
>>>> updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
>>>> with the FGT2 registers.
>>>
>>> Isn't that this series[1]? Should that have come first, I guess I know
>>> that *now*.
>> [...]
>>> [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
>>
>> It's not any clearer to me. Does this series depend on the 46-patch one?
>> Or, if we had the other, is this no longer needed? Or none of these,
>> they are independent.
> 
> They are independent. I think ideally we'd want everything landing at
> the same time, but we're past ideal at this point. Without this
> series, if someone uses PMU on v8.9 and firmware enabled FGT2, then
> the kernel will crash. Without the above series, KVM will have
> warnings in the kernel log, but otherwise function.

Right, they are independent. Just that Rob had observed this PMU v3.8 boot
requirement while reviewing the HW breakpoint series earlier. I should just
respin this series after the upcoming v6.14-rc1 release is out ?

Re: [PATCH 0/7] arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9

[Catalin Marinas]

On Tue, Jan 28, 2025 at 02:41:17PM +0530, Anshuman Khandual wrote:
> On 1/18/25 03:37, Rob Herring wrote:
> > On Thu, Jan 16, 2025 at 9:32 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> >>
> >> On Wed, Jan 08, 2025 at 07:47:16AM -0600, Rob Herring wrote:
> >>> On Wed, Jan 8, 2025 at 5:15 AM Marc Zyngier <maz@kernel.org> wrote:
> >>>> On Tue, 07 Jan 2025 22:13:47 +0000,
> >>>> Rob Herring <robh@kernel.org> wrote:
> >>>>> On Tue, Jan 7, 2025 at 6:13 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> >>>>>> But does KVM actually expose the feature to EL1 in ID_AA64DFR1_EL1 and
> >>>>>> than traps it at EL2?
> >>>>>
> >>>>> As Marc pointed out KVM only advertises PMUv3.8. Regardless, guest
> >>>>> accesses to these registers are trapped with or without this series.
> >>>>
> >>>> And most probably generates a nice splat in the kernel log, as nobody
> >>>> updated KVM to handle *correctly* PMICNTR_EL0 traps, let alone deal
> >>>> with the FGT2 registers.
> >>>
> >>> Isn't that this series[1]? Should that have come first, I guess I know
> >>> that *now*.
> >> [...]
> >>> [1] https://lore.kernel.org/all/20241210055311.780688-1-anshuman.khandual@arm.com/
> >>
> >> It's not any clearer to me. Does this series depend on the 46-patch one?
> >> Or, if we had the other, is this no longer needed? Or none of these,
> >> they are independent.
> > 
> > They are independent. I think ideally we'd want everything landing at
> > the same time, but we're past ideal at this point. Without this
> > series, if someone uses PMU on v8.9 and firmware enabled FGT2, then
> > the kernel will crash. Without the above series, KVM will have
> > warnings in the kernel log, but otherwise function.
> 
> Right, they are independent. Just that Rob had observed this PMU v3.8 boot
> requirement while reviewing the HW breakpoint series earlier. I should just
> respin this series after the upcoming v6.14-rc1 release is out ?

They may apply cleanly but please do rebase and repost at -rc1. Thanks.

-- 
Catalin