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Fri, 17 Jan 2025 14:11:15 -0800 Date: Fri, 17 Jan 2025 14:11:15 -0800 From: Nicolin Chen To: Jason Gunthorpe , CC: , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 08/14] iommufd/viommu: Add iommufd_viommu_report_event helper Message-ID: References: <20250110174132.GH396083@nvidia.com> <20250110195114.GJ5556@nvidia.com> <20250113192144.GT5556@nvidia.com> <20250113195433.GV5556@nvidia.com> <20250114134158.GC5556@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250114134158.GC5556@nvidia.com> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E8:EE_|MW5PR12MB5650:EE_ X-MS-Office365-Filtering-Correlation-Id: 2554ccde-1bf1-4506-02a1-08dd3743ea68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|1800799024|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2025 22:11:39.0718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2554ccde-1bf1-4506-02a1-08dd3743ea68 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5650 On Tue, Jan 14, 2025 at 09:41:58AM -0400, Jason Gunthorpe wrote: > On Mon, Jan 13, 2025 at 12:44:37PM -0800, Nicolin Chen wrote: > > IOMMU_VEVENT_HEADER_FLAGS_OVERFLOW = (1 << 0), > > }; > > > > struct iommufd_vevent_header_v1 { > > __u64 flags; > > __u32 num_events; > > __u32 num_overflows; // valid if flag_overflow is set > > }; > > num_overflows is hard, I'd just keep a counter. Ack. How does this look overall? @@ -1013,6 +1013,33 @@ struct iommu_ioas_change_process { #define IOMMU_IOAS_CHANGE_PROCESS \ _IO(IOMMUFD_TYPE, IOMMUFD_CMD_IOAS_CHANGE_PROCESS) +/** + * enum iommu_veventq_state - state for struct iommufd_vevent_header + * @IOMMU_VEVENTQ_STATE_OK: vEVENTQ is running + * @IOMMU_VEVENTQ_STATE_OVERFLOW: vEVENTQ is overflowed + */ +enum iommu_veventq_state { + IOMMU_VEVENTQ_STATE_OK = (1 << 0), + IOMMU_VEVENTQ_STATE_OVERFLOW = (1 << 1), +}; + +/** + * struct iommufd_vevent_header - Virtual Event Header for a vEVENTQ Status + * @state: One of enum iommu_veventq_state + * @counter: A counter reflecting the state of the vEVENTQ + * + * ---------------------------------------------------------------------------- + * | @state | @counter | + * ---------------------------------------------------------------------------- + * | IOMMU_VEVENTQ_STATE_OK | number of readable vEVENTs in the vEVENTQ | + * | IOMMU_VEVENTQ_STATE_OVERFLOW | number of missed vEVENTs since overflow | + * ---------------------------------------------------------------------------- + */ +struct iommufd_vevent_header { + __u32 state; + __u32 counter; +}; + /** * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use @@ -1050,6 +1077,13 @@ struct iommu_vevent_arm_smmuv3 { * * Explicitly allocate a virtual event queue interface for a vIOMMU. A vIOMMU * can have multiple FDs for different types, but is confined to one per @type. + * User space should open the @out_veventq_fd to read vEVENTs out of a vEVENTQ, + * if there are vEVENTs available. A vEVENTQ will overflow if the number of the + * vEVENTs hits @veventq_depth. + * + * Each vEVENT in a vEVENTQ encloses a struct iommufd_vevent_header followed by + * a type-specific data structure. The iommufd_vevent_header reports the status + * of the vEVENTQ when the vEVENT is added to the vEVENTQ. */ struct iommu_veventq_alloc { __u32 size;