From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32860C41513 for ; Fri, 11 Aug 2023 15:32:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236514AbjHKPcT (ORCPT ); Fri, 11 Aug 2023 11:32:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236500AbjHKPcT (ORCPT ); Fri, 11 Aug 2023 11:32:19 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DC9319A5; Fri, 11 Aug 2023 08:32:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 214DE65E9D; Fri, 11 Aug 2023 15:32:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AD3E1C433C7; Fri, 11 Aug 2023 15:32:12 +0000 (UTC) Date: Fri, 11 Aug 2023 16:32:10 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy , "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v4 18/36] arm64/gcs: Context switch GCS state for EL0 Message-ID: References: <20230807-arm64-gcs-v4-0-68cfa37f9069@kernel.org> <20230807-arm64-gcs-v4-18-68cfa37f9069@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230807-arm64-gcs-v4-18-68cfa37f9069@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-doc@vger.kernel.org On Mon, Aug 07, 2023 at 11:00:23PM +0100, Mark Brown wrote: > @@ -271,12 +272,31 @@ static void flush_tagged_addr_state(void) > clear_thread_flag(TIF_TAGGED_ADDR); > } > > +#ifdef CONFIG_ARM64_GCS > + > +static void flush_gcs(void) > +{ > + if (system_supports_gcs()) { Nitpick: use "if (system_supports_gcs()) return" when we have more than a line in the conditional block (slightly more consistent with other places). > + gcs_free(current); > + current->thread.gcs_el0_mode = 0; > + write_sysreg_s(0, SYS_GCSCRE0_EL1); > + write_sysreg_s(0, SYS_GCSPR_EL0); > + } > +} Do we need and isb() or there's one on this path? If it's only EL0 making use of this register, we should be fine with the ERET before returning to user. Not sure whether the kernel uses this, GCSSTTR doesn't need it. > +static void gcs_thread_switch(struct task_struct *next) > +{ > + if (!system_supports_gcs()) > + return; > + > + gcs_preserve_current_state(); > + > + /* > + * Ensure that GCS changes are observable by/from other PEs in > + * case of migration. > + */ > + if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next)) > + gcsb_dsync(); What's this barrier for? The spec (at least the version I have) only talks about accesses, nothing to do with the registers that we context switch here. -- Catalin