From: Mark Rutland <mark.rutland@arm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "Jonas Oberhauser" <jonas.oberhauser@huaweicloud.com>,
"Christoph Muellner" <christoph.muellner@vrull.eu>,
linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Shuah Khan" <shuah@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
"Anup Patel" <apatel@ventanamicro.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Guo Ren" <guoren@kernel.org>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Bj\"orn T\"opel" <bjorn@rivosinc.com>,
"Alan Stern" <stern@rowland.harvard.edu>,
"Andrea Parri" <parri.andrea@gmail.com>,
"Will Deacon" <will@kernel.org>,
"Daniel Lustig" <dlustig@nvidia.com>
Subject: Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support
Date: Mon, 27 Nov 2023 12:14:13 +0000 [thread overview]
Message-ID: <ZWSIFV9JGc-Mysvh@FVFF77S0Q05N> (raw)
In-Reply-To: <20231124115430.GS3818@noisy.programming.kicks-ass.net>
On Fri, Nov 24, 2023 at 12:54:30PM +0100, Peter Zijlstra wrote:
> On Fri, Nov 24, 2023 at 12:04:09PM +0100, Jonas Oberhauser wrote:
> > > I think ARM64 approached this problem by adding the
> > > load-acquire/store-release instructions and for TSO based code,
> > > translate into those (eg. x86 -> arm64 transpilers).
> >
> > Although those instructions have a bit more ordering constraints.
> >
> > I have heard rumors that the apple chips also have a register that can be
> > set at runtime.
>
> Oh, I thought they made do with the load-acquire/store-release thingies.
> But to be fair, I haven't been paying *that* much attention to the apple
> stuff.
>
> I did read about how they fudged some of the x86 flags thing.
I don't know what others may have built specifically, but architecturally on
arm64 we expect people to express ordering requirements through instructions.
ARMv8.0 has load-acquire and store-release, ARMv8.3 added RCpc forms of
load-acquire as part of FEAT_LRCPC, and ARMv8.4 added a number of instructions
as part of FEAT_LRCPC2.
For a number of reasons we avoid IMPLEMENTATION DEFINED controls for things
like this.
Thanks
Mark.
next prev parent reply other threads:[~2023-11-27 12:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-24 7:21 [RFC PATCH 0/5] RISC-V: Add dynamic TSO support Christoph Muellner
2023-11-24 7:21 ` [RFC PATCH 1/5] RISC-V: Add basic Ssdtso support Christoph Muellner
2023-11-24 7:21 ` [RFC PATCH 2/5] RISC-V: Expose Ssdtso via hwprobe API Christoph Muellner
2023-11-27 14:32 ` Samuel Holland
2023-11-27 14:36 ` Christoph Müllner
2023-11-24 7:21 ` [RFC PATCH 3/5] uapi: prctl: Add new prctl call to set/get the memory consistency model Christoph Muellner
2023-11-24 7:21 ` [RFC PATCH 4/5] RISC-V: Implement " Christoph Muellner
2023-11-24 7:21 ` [RFC PATCH 5/5] RISC-V: selftests: Add DTSO tests Christoph Muellner
2023-11-24 10:15 ` [RFC PATCH 0/5] RISC-V: Add dynamic TSO support Peter Zijlstra
2023-11-24 10:53 ` Christoph Müllner
2023-11-24 11:49 ` Peter Zijlstra
[not found] ` <59da3e41-abb3-405a-8f98-c74bdf26935b@huaweicloud.com>
2023-11-24 11:54 ` Peter Zijlstra
2023-11-24 13:05 ` Michael Ellerman
2023-11-26 12:34 ` Guo Ren
2023-11-27 12:14 ` Mark Rutland [this message]
2024-02-08 11:10 ` Andrea Parri
2023-11-25 2:51 ` Guo Ren
2023-11-27 11:16 ` Peter Zijlstra
2023-11-28 1:42 ` Guo Ren
2023-11-27 10:36 ` Conor Dooley
2023-11-27 12:58 ` Christoph Müllner
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