From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oo1-f43.google.com (mail-oo1-f43.google.com [209.85.161.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5298E4402 for ; Sat, 6 Jan 2024 03:52:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="oB1wZTXN" Received: by mail-oo1-f43.google.com with SMTP id 006d021491bc7-59822d59158so124344eaf.3 for ; Fri, 05 Jan 2024 19:52:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1704513178; x=1705117978; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=X2aOIl4UNnpRK6RyeoDnHpQHzACVL3QRju2SnuNTBm0=; b=oB1wZTXN8MruiWXHtaPpZkFJlPviDCbnZkvZoriNCUHDVJVMGBtuvddGG7R7kVJ8jj j8olInbE6OiS2D90BsVp3j/CyvKHouXnUpr9mqF+7M7KU9qEsHUyiWn88p8CcJWLteRY 5XPLwO5Uj0LcaWGTtqEF8zMuyGBfg/jNqRO06B4JmrlFafEm07xUvZOTL4HFlve+V7Y8 afPLs+B5gVcu5yzBHHJYnbzO3iWY6RrFFQoMMa1YxB0k0R+Csa5fHrthla74pZG16GHN 3o2/mbaqIK2MxLgnRzcalCdg6h8XITAYkLFjqxso0Y2VgmgvUBObL3YyWG2DGIZonB4v Uiyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704513178; x=1705117978; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=X2aOIl4UNnpRK6RyeoDnHpQHzACVL3QRju2SnuNTBm0=; b=aEfbtouiyYmQwDZ2aHLH5PwHfOEEl9F64HSkRzut3H46GLptGcFonYYRJiGyH36GEr i6aSr0CavToSRdU/pd/9gBDR9v44Oa1VxM95LG12tBEvF4Y6vBEvXbomXjO1QVU5gjnA 4oBJBJ7zvaKq1wc/SOvZaGDXvPwMtaI4xSVyUdq43EsGF9OjTjJ1eQ02iS7n5R7DpmAb wiaJk2YFRB84KhoAzONfKNTHmBIFMmZgePq/Bmo3BnZONMmTV12TVHGIW8K+fbfOTGsY dmfWA7mNi+AVSrkFkugRPqZtL5XQ8qFHKioickgfEnhFw0G7qRZFNZuEvvP3JSsGIDKH 5q1Q== X-Gm-Message-State: AOJu0YyYnF7ElzOhZlMvLcZ26lo1DUUx5z+itLpRbRoNO4AU66W9VQQP bBNW5bfgIVYcpV0A1gw+l6BzJbYJgggBlg== X-Google-Smtp-Source: AGHT+IFZdiX5/Chz2pb3J2lpmWZK0wj7liYYlV3sycKkqbhQFnl4yRMsyYKAzwdDC9bujM3U8Qb0KA== X-Received: by 2002:a05:6358:4406:b0:172:e3d3:4906 with SMTP id z6-20020a056358440600b00172e3d34906mr489239rwc.34.1704513178245; Fri, 05 Jan 2024 19:52:58 -0800 (PST) Received: from ghost ([2601:647:5700:6860:73c:7a5f:bc03:fe77]) by smtp.gmail.com with ESMTPSA id mv2-20020a17090b198200b0028c361b5c7csm2079193pjb.23.2024.01.05.19.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Jan 2024 19:52:57 -0800 (PST) Date: Fri, 5 Jan 2024 19:52:55 -0800 From: Charlie Jenkins To: Atish Patra Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: Re: [PATCH v3 2/2] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl Message-ID: References: <20231213-fencei-v3-0-b75158238eb7@rivosinc.com> <20231213-fencei-v3-2-b75158238eb7@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Jan 05, 2024 at 06:52:12PM -0800, Atish Patra wrote: > On Wed, Dec 13, 2023 at 2:48 PM Charlie Jenkins wrote: > > > > Provide documentation that explains how to properly do CMODX in riscv. > > > > Signed-off-by: Charlie Jenkins > > --- > > Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++++++ > > Documentation/arch/riscv/index.rst | 1 + > > 2 files changed, 99 insertions(+) > > > > diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst > > new file mode 100644 > > index 000000000000..20f327d85116 > > --- /dev/null > > +++ b/Documentation/arch/riscv/cmodx.rst > > @@ -0,0 +1,98 @@ > > +.. SPDX-License-Identifier: GPL-2.0 > > + > > +============================================================================== > > +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux > > +============================================================================== > > + > > +CMODX is a programming technique where a program executes instructions that were > > +modified by the program itself. Instruction storage and the instruction cache > > +(icache) is not guaranteed to be synchronized on RISC-V hardware. Therefore, the > > +program must enforce its own synchonization with the unprivileged fence.i/ > > /s/synchonization/synchronization > > > +instruction. > > + > > +However, the default Linux ABI prohibits the use of fence.i in userspace > > +applications. At any point the scheduler may migrate a task onto a new hart. If > > +migration occurs after the userspace synchronized the icache and instruction > > +storage with fence.i, the icache will no longer be clean. This is due to the > > +behavior of fence.i only affecting the hart that it is called on. Thus, the hart > > +that the task has been migrated to, may not have synchronized instruction > > +storage and icache. > > + > > +There are two ways to solve this problem: use the riscv_flush_icache() syscall, > > +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl(). The syscall should be used > > +when the application very rarely needs to flush the icache. If the icache will > > The syscall is a one time operation while prctl is sticky. > It would be great if we can add a little more context why the syscall > behaves this way compared to prctl. I can highlight the point that the prctl is sticky and the syscall is not. As for "why", they simply fill different roles. It is useful to have both a sticky and a non-sticky option. I chose the sticky operation to be a prctl rather than a generic syscall because the semantics of prctl is that they operate on process or thread scoped behavior which is what was needed. - Charlie > > > +need to be flushed many times in the lifetime of the application, the prctl > > +should be used. > > + > > +The prctl informs the kernel that it must emit synchronizing instructions upon > > +task migration. The program itself must emit synchonizing instructions when > > /s/synchonizing/synchronizing > > > +necessary as well. > > + > > +1. prctl() Interface > > +--------------------- > > + > > +Before the program emits their first icache flushing instruction, the program > > +must call this prctl(). > > + > > +* prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX, unsigned long ctx, unsigned long per_thread) > > + > > + Sets the icache flushing context. If per_thread is 0, context will be > > + applied per process, otherwise if per_thread is 1 context will be > > + per-thread. Any other number will have undefined behavior. > > + > > + * :c:macro:`PR_RISCV_CTX_SW_FENCEI`: Allow fence.i to be called in > > + userspace. > > + > > +Example usage: > > + > > +The following files are meant to be compiled and linked with each other. The > > +modify_instruction() function replaces an add with 0 with an add with one, > > +causing the instruction sequence in get_value() to change from returning a zero > > +to returning a one. > > + > > +cmodx.c:: > > + > > + #include > > + #include > > + > > + extern int get_value(); > > + extern void modify_instruction(); > > + > > + int main() > > + { > > + int value = get_value(); > > + printf("Value before cmodx: %d\n", value); > > + > > + // Call prctl before first fence.i is called inside modify_instruction > > + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX, PR_RISCV_CTX_SW_FENCEI, 0); > > + modify_instruction(); > > + > > + value = get_value(); > > + printf("Value after cmodx: %d\n", value); > > + return 0; > > + } > > + > > +cmodx.S:: > > + > > + .option norvc > > + > > + .text > > + .global modify_instruction > > + modify_instruction: > > + lw a0, new_insn > > + lui a5,%hi(old_insn) > > + sw a0,%lo(old_insn)(a5) > > + fence.i > > + ret > > + > > + .section modifiable, "awx" > > + .global get_value > > + get_value: > > + li a0, 0 > > + old_insn: > > + addi a0, a0, 0 > > + ret > > + > > + .data > > + new_insn: > > + addi a0, a0, 1 > > diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/index.rst > > index 4dab0cb4b900..eecf347ce849 100644 > > --- a/Documentation/arch/riscv/index.rst > > +++ b/Documentation/arch/riscv/index.rst > > @@ -13,6 +13,7 @@ RISC-V architecture > > patch-acceptance > > uabi > > vector > > + cmodx > > > > features > > > > > > -- > > 2.43.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > -- > Regards, > Atish