From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1E95AD51; Sun, 13 Apr 2025 07:54:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744530862; cv=none; b=Sbza91Im2DvrmMmBWmdudUcml3dOSvPdXC2Hb8LqLROb3M9UrzKw1r7X3khOr5yvy9zABVKSt3mKLMYJi1lXCA/JJ4K1QFHlainZgqoD2iTTygYnNvGN4YrTpKjtzO2MvUdiwTlC4G15I+F6s1f1gUIlzDsAAZ+3V1Qpfju1vS4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744530862; c=relaxed/simple; bh=HaMA3Kl+meGFuUQOS/ZfEYd8wtkz83n+WzSGOOL5TFo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=OybxDci3mHWTgR1+OZnCt+7Vby6idbTHOxaom/Ut1c5oNZNNKWVAJd4EBcsiLASPLJu+wIpLRDKICHJy849NdRgivRA+t6dGW5FHbclkFvcl/e619ALtDkPhamLUg9lQXXRXi6DTT0tvc5uV2i3D2cX7DhKY8qfgJL6UKWUNx64= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AinuOW0E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AinuOW0E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DB1DC4CEDD; Sun, 13 Apr 2025 07:54:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744530862; bh=HaMA3Kl+meGFuUQOS/ZfEYd8wtkz83n+WzSGOOL5TFo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=AinuOW0EIqPjYFPMwEsVSBNrmH7DDwhnxqqRjuIb45I0zKaxjlTNknmDUXsbY4NST hCjNSXnnCvPMFTYrcDJEjxSa7Qx+5P8mx0c6zVBlwKDsdBhOP2+r8cUZ4eftWXC+Yh Kb3ecfFoirp9ZjMSkB62uAb27onn9Mg0/hwMTtvQkR68gKAELQ7C/1MURxG8CukIL3 MK1lpwC40ehUTsoZYRnV8To6TYopbh8L/1Od7XeubxWr9MhprsS1zqDXLhY3GxzlRM tFtLuKNu/gtVDVkKtPpR1Sgy0owxRmXumFb1o1gvWq5ljYOtPtI5bbQm0MoxAR/4nv 7N+9aosY45TpA== Date: Sun, 13 Apr 2025 09:54:15 +0200 From: Ingo Molnar To: Borislav Petkov Cc: Mario Limonciello , Jean Delvare , Andi Shyti , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Jonathan Corbet , Mario Limonciello , Yazen Ghannam , Thomas Gleixner , Ingo Molnar , Dave Hansen , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , Shyam Sundar S K , Hans de Goede , "open list:DOCUMENTATION" , open list , "open list:I2C/SMBUS CONTROLLER DRIVERS FOR PC" , "open list:AMD PMC DRIVER" Subject: Re: [PATCH v3 2/4] i2c: piix4: Move SB800_PIIX4_FCH_PM_ADDR definition to amd_node.h Message-ID: References: <20250410200202.2974062-1-superm1@kernel.org> <20250410200202.2974062-3-superm1@kernel.org> <20250411114908.GLZ_kBtN94h79EEN6j@fat_crate.local> <20250411124157.GDZ_kOFfsGgY4zUXA5@fat_crate.local> <5509f044-912b-4d10-bdeb-95ec52002b06@kernel.org> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: * Borislav Petkov wrote: > On April 12, 2025 10:15:27 PM GMT+02:00, Ingo Molnar wrote: > > > >* Mario Limonciello wrote: > > > >> SB800 is pre-Zen stuff. It's "before my time" - I guess that's the > >> precursor to FCH being in the SoC but has the same functionality. > >> > >> So I'm thinking . > > > >I went by the SB800_PIIX4_FCH_PM_ADDR name, which is a misnomer these > >days? > > > >But yeah, sounds good to me too. Boris? > > I was aiming more for a header which contains non-CPU defines - i.e., > platform. But the FCH is only one part of that platform. But let's > start with amd/fch.h - "amd/" subpath element would allow us to > trivially put other headers there too - and see where it gets us. We > can (and will) always refactor later if needed... Yeah, agreed on opening the namespace for this. Thanks, Ingo