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Thu, 25 Jan 2024 09:05:05 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id s19-20020a056a0008d300b006d9a6039745sm16078660pfu.40.2024.01.25.09.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 09:05:05 -0800 (PST) Date: Thu, 25 Jan 2024 09:05:01 -0800 From: Deepak Gupta To: David Hildenbrand Cc: rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, paul.walmsley@sifive.com, palmer@dabbelt.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, corbet@lwn.net, aou@eecs.berkeley.edu, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, shuah@kernel.org, brauner@kernel.org, guoren@kernel.org, samitolvanen@google.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, waylingii@gmail.com, greentime.hu@sifive.com, heiko@sntech.de, jszhang@kernel.org, shikemeng@huaweicloud.com, charlie@rivosinc.com, panqinglin2020@iscas.ac.cn, willy@infradead.org, vincent.chen@sifive.com, andy.chiu@sifive.com, gerg@kernel.org, jeeheng.sia@starfivetech.com, mason.huo@starfivetech.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bhe@redhat.com, chenjiahao16@huawei.com, ruscur@russell.cc, bgray@linux.ibm.com, alx@kernel.org, baruch@tkos.co.il, zhangqing@loongson.cn, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, joey.gouly@arm.com, shr@devkernel.io, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [RFC PATCH v1 08/28] mm: Define VM_SHADOW_STACK for RISC-V Message-ID: References: <20240125062739.1339782-1-debug@rivosinc.com> <20240125062739.1339782-9-debug@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: On Thu, Jan 25, 2024 at 09:17:01AM +0100, David Hildenbrand wrote: >On 25.01.24 07:21, debug@rivosinc.com wrote: >>From: Deepak Gupta >> >>VM_SHADOW_STACK is defined by x86 as vm flag to mark a shadow stack vma. >> >>x86 uses VM_HIGH_ARCH_5 bit but that limits shadow stack vma to 64bit only. >>arm64 follows same path >>https://lore.kernel.org/lkml/20231009-arm64-gcs-v6-12-78e55deaa4dd@kernel.org/#r >> >>On RISC-V, write-only page table encodings are shadow stack pages. This patch >>re-defines VM_WRITE only to be VM_SHADOW_STACK. >> >>Next set of patches will set guard rail that no other mm flow can set VM_WRITE >>only in vma except when specifically creating shadow stack. >> >>Signed-off-by: Deepak Gupta >>--- >> include/linux/mm.h | 14 +++++++++++++- >> 1 file changed, 13 insertions(+), 1 deletion(-) >> >>diff --git a/include/linux/mm.h b/include/linux/mm.h >>index 418d26608ece..dfe0e8118669 100644 >>--- a/include/linux/mm.h >>+++ b/include/linux/mm.h >>@@ -352,7 +352,19 @@ extern unsigned int kobjsize(const void *objp); >> * for more details on the guard size. >> */ >> # define VM_SHADOW_STACK VM_HIGH_ARCH_5 >>-#else >>+#endif >>+ >>+#ifdef CONFIG_RISCV_USER_CFI >>+/* >>+ * On RISC-V pte encodings for shadow stack is R=0, W=1, X=0 and thus RISCV >>+ * choosing to use similar mechanism on vm_flags where VM_WRITE only means >>+ * VM_SHADOW_STACK. RISCV as well doesn't support VM_SHADOW_STACK to be set >>+ * with VM_SHARED. >>+ */ >>+#define VM_SHADOW_STACK VM_WRITE >>+#endif >>+ >>+#ifndef VM_SHADOW_STACK >> # define VM_SHADOW_STACK VM_NONE >> #endif > >That just screams for trouble. Can we find a less hacky way, please? > >Maybe just start with 64bit support only and do it like the other >archs. No need to be special. > >When wanting to support 32bit, we'll just finally clean up this high >flag mess and allow for more vm flags on 32bit as well. Noted. I wanted to give a chance to anyone who cares about 32bit on riscv. Will fix it in next series. > >-- >Cheers, > >David / dhildenb >