From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D10BE13175B for ; Thu, 25 Jan 2024 17:54:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706205272; cv=none; b=RnRIYugSjRJil9ML5jHNusHNAOSECH8n2i+CQMWg0LbX26Fz5KuwDb07IB24f5WXWx6KljgIrPbL/4NH0M/qhUKCIuSPaL4TwyB/yKnh6ontlSx3RxfcwydeQTjvLHIGblNTMxN8rnnhwgv/apEl1z1mCMM7nScqyviKjOgYSE4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706205272; c=relaxed/simple; bh=VsLFSDl7f7nn/2y4Kg5VSlUgb504F1jxZ9Td7ivSykw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ow9MCLZbV/uWJdUWZU2M0x0x7771CxclAKwGNkcSN5xIPEFNHrF9hO2IA5ia/iNhtv0s8lqNdDeq2pF+ndUfqJQvZ9LpXH1hmFFixRom70MviWveG5ZSSOw9kRG9ITKkaVH/0eYcftX8o6K9AxD165MJPEZZyerSvAJLHKiCNbc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=Pz6dvobP; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Pz6dvobP" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-1d74678df08so30477735ad.1 for ; Thu, 25 Jan 2024 09:54:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1706205269; x=1706810069; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=2nicyzemtTRD4VSL2aIrfR13izgwrVMBCjiaMcBIu4g=; b=Pz6dvobP3bBpBIqYOwIRbPEQ0kDqPXzNkD24vhOcQZq61EZBwNBa1p2Rv9tIvMkVre wDGHea+x3L8tuQuSnLPbKEEUHu5wzVXFKA62wi1L6hn0S6Ep5grJ53EN+egkxjqxLW1t s+dPT8eBwdocV/D+MFYtKa65myLQXzuVM3hD+MPKKBHFXGPJOOMOE31W89jbrsWMmt3n FrKDUeTdb/9KlGFs5jzc3dlWHeAb3+Rkw7linE+GOZ3ZYiOEz+vR7pTpq1ISGfQ+FkAx /HV/z+7BI+M9OmUnadV/XqmTxrXMPe9B99qL/ubw5PXWSeBTPQVldsxo1dvJgY6DvrUx KmGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706205269; x=1706810069; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=2nicyzemtTRD4VSL2aIrfR13izgwrVMBCjiaMcBIu4g=; b=BD0SeoYFNC5vUfC/0YLlac8CLIq4ULgebDr+6bkaOsz8zfZ7P8+Sg3EbQxSNJsPVkq cbg2W4N0sf21DAXVr5xiUkIuqEt9G/ULt+56c10fq4Xvytpm0fIAlj3vLXop03q8l5hF Z0Tuuo/DaPCP+q/+mQis/ckOUqID5GOC5/eDNSuvQt1Io5Yx9NiBSUwppG88QFg3dbtR AH35jtCb10nkHl9QwEp+Ig4gDvxdKJdRqOhZVyD4b6Qv6E8CX6omWT9htpFZgO9RrrX3 rutFT1HU8IM1FHA/7HoihFVPQeSHNHE1FPpXYknU0a8qWvpOGroDCF23uEt3k9XOBRuD jemA== X-Gm-Message-State: AOJu0YxAzw7Gxcn+fV1IeW7fdCo6BxKtV9HBh+qr7689hWtCFI/Ns0T9 kPgQZ3i87ZZyPwQ0VPejl36DDoWqC9L7P10wf2VZGp8IIBaPGSJUX1ecomqUC2k= X-Google-Smtp-Source: AGHT+IHocjbJl+xR8mMLXKtkqWJu/nhVxybtwo7TBdSkwNgtnoPBjFJ6RTaIl5x14FjrIbULLsROeg== X-Received: by 2002:a17:903:124c:b0:1d7:eb1:a053 with SMTP id u12-20020a170903124c00b001d70eb1a053mr104655plh.18.1706205269113; Thu, 25 Jan 2024 09:54:29 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id u24-20020a170902a61800b001d74343a53dsm7538299plq.81.2024.01.25.09.54.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 09:54:28 -0800 (PST) Date: Thu, 25 Jan 2024 09:54:24 -0800 From: Deepak Gupta To: Stefan O'Rear Cc: rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, "kito.cheng@sifive.com" , Kees Cook , Andrew Jones , paul.walmsley@sifive.com, Palmer Dabbelt , Conor Dooley , cleger@rivosinc.com, Atish Patra , Alexandre Ghiti , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Alexandre Ghiti , Jonathan Corbet , Albert Ou , oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, "Eric W. Biederman" , shuah@kernel.org, Christian Brauner , guoren , samitolvanen@google.com, Evan Green , xiao.w.wang@intel.com, Anup Patel , mchitale@ventanamicro.com, waylingii@gmail.com, greentime.hu@sifive.com, Heiko Stuebner , Jisheng Zhang , shikemeng@huaweicloud.com, david@redhat.com, Charlie Jenkins , panqinglin2020@iscas.ac.cn, willy@infradead.org, Vincent Chen , Andy Chiu , Greg Ungerer , jeeheng.sia@starfivetech.com, mason.huo@starfivetech.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bhe@redhat.com, ruscur@russell.cc, bgray@linux.ibm.com, alx@kernel.org, baruch@tkos.co.il, zhangqing@loongson.cn, Catalin Marinas , revest@chromium.org, josh@joshtriplett.org, joey.gouly@arm.com, shr@devkernel.io, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [RFC PATCH v1 02/28] riscv: envcfg save and restore on trap entry/exit Message-ID: References: <20240125062739.1339782-1-debug@rivosinc.com> <20240125062739.1339782-3-debug@rivosinc.com> <23d023c0-27cf-44fa-be0a-000d1534ef86@app.fastmail.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: On Thu, Jan 25, 2024 at 09:09:14AM -0800, Deepak Gupta wrote: >On Thu, Jan 25, 2024 at 02:19:29AM -0500, Stefan O'Rear wrote: >>On Thu, Jan 25, 2024, at 1:21 AM, debug@rivosinc.com wrote: >>>From: Deepak Gupta >>> >>>envcfg CSR defines enabling bits for cache management instructions and soon >>>will control enabling for control flow integrity and pointer masking features. >>> >>>Control flow integrity enabling for forward cfi and backward cfi is controlled >>>via envcfg and thus need to be enabled on per thread basis. >>> >>>This patch creates a place holder for envcfg CSR in `thread_info` and adds >>>logic to save and restore on trap entry and exits. >> >>Should only be "restore"? I don't see saving. > >It's always saved in `thread_info` and user mode can't change it. >So no point saving it. Also I'll fix the commit message. I think that's what you were pointing out. > >> >>> >>>Signed-off-by: Deepak Gupta >>>--- >>> arch/riscv/include/asm/thread_info.h | 1 + >>> arch/riscv/kernel/asm-offsets.c | 1 + >>> arch/riscv/kernel/entry.S | 4 ++++ >>> 3 files changed, 6 insertions(+) >>> >>>diff --git a/arch/riscv/include/asm/thread_info.h >>>b/arch/riscv/include/asm/thread_info.h >>>index 574779900bfb..320bc899a63b 100644 >>>--- a/arch/riscv/include/asm/thread_info.h >>>+++ b/arch/riscv/include/asm/thread_info.h >>>@@ -57,6 +57,7 @@ struct thread_info { >>> long user_sp; /* User stack pointer */ >>> int cpu; >>> unsigned long syscall_work; /* SYSCALL_WORK_ flags */ >>>+ unsigned long envcfg; >>> #ifdef CONFIG_SHADOW_CALL_STACK >>> void *scs_base; >>> void *scs_sp; >>>diff --git a/arch/riscv/kernel/asm-offsets.c >>>b/arch/riscv/kernel/asm-offsets.c >>>index a03129f40c46..cdd8f095c30c 100644 >>>--- a/arch/riscv/kernel/asm-offsets.c >>>+++ b/arch/riscv/kernel/asm-offsets.c >>>@@ -39,6 +39,7 @@ void asm_offsets(void) >>> OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); >>> OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp); >>> OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp); >>>+ OFFSET(TASK_TI_ENVCFG, task_struct, thread_info.envcfg); >>> #ifdef CONFIG_SHADOW_CALL_STACK >>> OFFSET(TASK_TI_SCS_SP, task_struct, thread_info.scs_sp); >>> #endif >>>diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S >>>index 54ca4564a926..63c3855ba80d 100644 >>>--- a/arch/riscv/kernel/entry.S >>>+++ b/arch/riscv/kernel/entry.S >>>@@ -129,6 +129,10 @@ SYM_CODE_START_NOALIGN(ret_from_exception) >>> addi s0, sp, PT_SIZE_ON_STACK >>> REG_S s0, TASK_TI_KERNEL_SP(tp) >>> >>>+ /* restore envcfg bits for current thread */ >>>+ REG_L s0, TASK_TI_ENVCFG(tp) >>>+ csrw CSR_ENVCFG, s0 >>>+ >> >>This is redundant if we're repeatedly processing interrupts or exceptions >>within a single task. We should only be writing envcfg when switching >>between tasks or as part of the prctl. >> >>We need to use an ALTERNATIVE for this since the oldest supported hardware >>does not have envcfg csrs. > >Yeah fixing that in next series. Thanks > >> >>-s >> >>> /* Save the kernel shadow call stack pointer */ >>> scs_save_current >>> >>>-- >>>2.43.0 >>> >>> >>>_______________________________________________ >>>linux-riscv mailing list >>>linux-riscv@lists.infradead.org >>>http://lists.infradead.org/mailman/listinfo/linux-riscv