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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240501-moneyless-shifter-a54bbaecc4e7@spud> On Wed, May 01, 2024 at 07:09:28PM +0100, Conor Dooley wrote: > On Wed, May 01, 2024 at 07:03:46PM +0100, Conor Dooley wrote: > > On Wed, May 01, 2024 at 10:51:38AM -0700, Charlie Jenkins wrote: > > > On Wed, May 01, 2024 at 09:44:15AM -0700, Evan Green wrote: > > > > On Fri, Apr 26, 2024 at 2:29 PM Charlie Jenkins wrote: > > > > > + for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) { > > > > > + const struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i]; > > > > > + > > > > > + if (bitmap_empty(ext_list->vendor_bitmap, ext_list->bitmap_size)) > > > > > + bitmap_copy(ext_list->vendor_bitmap, > > > > > + ext_list->per_hart_vendor_bitmap[cpu].isa, > > > > > + ext_list->bitmap_size); > > > > > > > > Could you get into trouble here if the set of vendor extensions > > > > reduces to zero, and then becomes non-zero? To illustrate, consider > > > > these masks: > > > > cpu 0: 0x0000C000 > > > > cpu 1: 0x00000003 <<< vendor_bitmap ANDs out to 0 > > > > cpu 2: 0x00000010 <<< oops, we end up copying this into vendor_bitmap > > > > > > > > > > Huh that's a good point. The standard extensions have that same bug too? > > > > > > if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) > > > bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); > > > else > > > bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); > > > > I suppose it could in theory, but the boot hart needs ima to even get > > this far. I think you'd only end up with this happening if there were > > enabled harts that supported rvXXe, but I don't think we even add those > > to the possible set of CPUs. I'll have to check. > > Ye, you don't get marked possible if you don't have ima, so I don't > think this is possible to have happen. Maybe a comment here is > sufficient, explaining why this cannot reduce to zeros? Okay cool. A comment is sufficient then. - Charlie > >