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AJvYcCVWNdoXcKat/i/CGR3TdKGG6s1TgKMsg0j7q2vw69QQu8CMp18eHC7hc8MG0XwBYBYoIRqpZMYIc2hUoPTflwpnUi8lAJbfzoE3 X-Gm-Message-State: AOJu0YxRrJEudpGN9EbRezILYHSi49J0JpnTPO7kcelDUYerAND5Srqj 94cSS8yz68XWp2f8Gz+rNamxv27wk3uCyGLloXaKlotsF75pQCa+APmds+VWyz8= X-Google-Smtp-Source: AGHT+IFn88bAR8FRppjVpxx4Li1DASVwJ1zF7Yvk7MQzB0h8bmxFN5sOCIHGIBoohUfrAWiBfqn16Q== X-Received: by 2002:aa7:8b11:0:b0:6f0:be31:8577 with SMTP id d2e1a72fcca58-6f49c280ad8mr4602857b3a.22.1715213255357; Wed, 08 May 2024 17:07:35 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:4144:6911:574f:fec1]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f4d2b2fe07sm137325b3a.216.2024.05.08.17.07.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 17:07:34 -0700 (PDT) Date: Wed, 8 May 2024 17:07:30 -0700 From: Charlie Jenkins To: Andy Chiu Cc: Deepak Gupta , paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org, corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: Re: [PATCH v3 05/29] riscv: zicfiss / zicfilp enumeration Message-ID: References: <20240403234054.2020347-1-debug@rivosinc.com> <20240403234054.2020347-6-debug@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, May 09, 2024 at 08:00:00AM +0800, Andy Chiu wrote: > Hi Deepak, > > On Thu, Apr 4, 2024 at 7:41 AM Deepak Gupta wrote: > > > > This patch adds support for detecting zicfiss and zicfilp. zicfiss and > > zicfilp stands for unprivleged integer spec extension for shadow stack > > and branch tracking on indirect branches, respectively. > > > > This patch looks for zicfiss and zicfilp in device tree and accordinlgy > > lights up bit in cpu feature bitmap. Furthermore this patch adds detection > > utility functions to return whether shadow stack or landing pads are > > supported by cpu. > > > > Signed-off-by: Deepak Gupta > > --- > > arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ > > arch/riscv/include/asm/hwcap.h | 2 ++ > > arch/riscv/include/asm/processor.h | 1 + > > arch/riscv/kernel/cpufeature.c | 2 ++ > > 4 files changed, 18 insertions(+) > > > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > > index 0bd11862b760..f0fb8d8ae273 100644 > > --- a/arch/riscv/include/asm/cpufeature.h > > +++ b/arch/riscv/include/asm/cpufeature.h > > @@ -8,6 +8,7 @@ > > > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi > > > > DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); > > > > +static inline bool cpu_supports_shadow_stack(void) > > +{ > > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && > > + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); > > +} > > + > > +static inline bool cpu_supports_indirect_br_lp_instr(void) > > +{ > > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && > > + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); > > +} > > + > > #endif > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 1f2d2599c655..74b6c727f545 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -80,6 +80,8 @@ > > #define RISCV_ISA_EXT_ZFA 71 > > #define RISCV_ISA_EXT_ZTSO 72 > > #define RISCV_ISA_EXT_ZACAS 73 > nit: two tabs for alignment > Deepak, I think you might be using tabs with a display size of 4 spaces that causes a couple of places to have incorrect alignment but would look correct with 4 spaces. Linux uses 8 spaces for tabs. - Charlie > > > +#define RISCV_ISA_EXT_ZICFILP 74 > > +#define RISCV_ISA_EXT_ZICFISS 75 > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > > index a8509cc31ab2..6c5b3d928b12 100644 > > --- a/arch/riscv/include/asm/processor.h > > +++ b/arch/riscv/include/asm/processor.h > > @@ -13,6 +13,7 @@ > > #include > > > > #include > > +#include > > > > #ifdef CONFIG_64BIT > > #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 79a5a35fab96..d052cad5b82f 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), > > __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), > > __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), > > + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts), > > + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts), > > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), > > __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), > > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), > > -- > > 2.43.2 > > > > Thanks, > Andy