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AJvYcCUXE193Uufn7wacIPSB6VrKWERvUBm1c2DNiQfCGejjd/iCdxf9bF6jTWvaKOw9Ww1EbixMRZ1u8NQPFcp5zUKAMs9/WAgT/yXi X-Gm-Message-State: AOJu0YyPATRRk3+cxdLeeQvr56jDvYKAPZXcE5VAUuPFt72Sx3/FbkA4 jXk0aRmNsvOgLnuAoUzUa1ZNowmxTM8ZjuY60f8RL4j3R0N+MUczgdDMxyT7taQ= X-Google-Smtp-Source: AGHT+IFnbLXicXE+Y/UKuSVClJLtlfBWO7CdnrEkpjnDppDvuoBtNhLdA/briBDaFchoAw9tI2ob0A== X-Received: by 2002:a17:902:f68e:b0:1e4:c07b:a8e0 with SMTP id d9443c01a7336-1ef441a76fcmr123301465ad.66.1715625235664; Mon, 13 May 2024 11:33:55 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0bf32b4dsm84209665ad.137.2024.05.13.11.33.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 11:33:55 -0700 (PDT) Date: Mon, 13 May 2024 11:33:50 -0700 From: Deepak Gupta To: Charlie Jenkins Cc: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org, corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: Re: [PATCH v3 02/29] riscv: define default value for envcfg for task Message-ID: References: <20240403234054.2020347-1-debug@rivosinc.com> <20240403234054.2020347-3-debug@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: On Fri, May 10, 2024 at 03:33:36PM -0700, Charlie Jenkins wrote: >On Wed, Apr 03, 2024 at 04:34:50PM -0700, Deepak Gupta wrote: >> Defines a base default value for envcfg per task. By default all tasks >> should have cache zeroing capability. Any future base capabilities that >> apply to all tasks can be turned on same way. >> >> Signed-off-by: Deepak Gupta >> --- >> arch/riscv/include/asm/csr.h | 2 ++ >> arch/riscv/kernel/process.c | 6 ++++++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >> index 2468c55933cd..bbd2207adb39 100644 >> --- a/arch/riscv/include/asm/csr.h >> +++ b/arch/riscv/include/asm/csr.h >> @@ -202,6 +202,8 @@ >> #define ENVCFG_CBIE_FLUSH _AC(0x1, UL) >> #define ENVCFG_CBIE_INV _AC(0x3, UL) >> #define ENVCFG_FIOM _AC(0x1, UL) >> +/* by default all threads should be able to zero cache */ >> +#define ENVCFG_BASE ENVCFG_CBZE >> >> /* Smstateen bits */ >> #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 >> diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c >> index 92922dbd5b5c..d3109557f951 100644 >> --- a/arch/riscv/kernel/process.c >> +++ b/arch/riscv/kernel/process.c >> @@ -152,6 +152,12 @@ void start_thread(struct pt_regs *regs, unsigned long pc, >> else >> regs->status |= SR_UXL_64; >> #endif >> + /* >> + * read current envcfg settings, AND it with base settings applicable >> + * for all the tasks. Base settings should've been set up during CPU >> + * bring up. >> + */ >> + current->thread_info.envcfg = csr_read(CSR_ENVCFG) & ENVCFG_BASE; > >This needs to be gated on xlinuxenvcfg. You're right. This csr read should be gated on xlinuxenvcfg. Will fix it. > >- Charlie > >> } >> >> void flush_thread(void) >> -- >> 2.43.2 >>