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AJvYcCWZQJ5p3d0UX//q9fSSqYCoI7xqNNn9MN86JyIoGhgmISrkqCZbWH87oAEWUv69qBaTYgseDv4C+OtOKOqs13k3V1CrkgUPvIh3 X-Gm-Message-State: AOJu0YwfmHenmcSD0AXPf7AE6E/sN9+XyERKxELPWeIp3XtVB0v0oC1a HKhNByg57vk2tJoLf8E2nbnKuYwnihCJENBePluByB8xFhTiasmmxXOXZKf9bYc= X-Google-Smtp-Source: AGHT+IEborn6L609viyJY6HL00IRTeefiOYqFrtGZGbG+Un7sype/7J809TXJhOL2x2fa0cmRNR4eg== X-Received: by 2002:a05:6a20:5647:b0:1ad:5325:d9b7 with SMTP id adf61e73a8af0-1b26460b6bbmr2226154637.52.1717082746244; Thu, 30 May 2024 08:25:46 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7022b6c6047sm1848587b3a.46.2024.05.30.08.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 08:25:45 -0700 (PDT) Date: Thu, 30 May 2024 08:25:42 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v5 09/16] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions Message-ID: References: <20240517145302.971019-1-cleger@rivosinc.com> <20240517145302.971019-10-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240517145302.971019-10-cleger@rivosinc.com> On Fri, May 17, 2024 at 04:52:49PM +0200, Clément Léger wrote: > Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe. > > Signed-off-by: Clément Léger > --- > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++++++++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ > arch/riscv/kernel/sys_hwprobe.c | 4 ++++ > 3 files changed, 28 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 48be38e0b788..cad84f51412d 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -196,6 +196,26 @@ The following keys are defined: > supported as defined in the RISC-V ISA manual starting from commit > 58220614a5f ("Zimop is ratified/1.0"). > > + * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 3b16a12204b1..652b2373729f 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -61,6 +61,10 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) > #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36) > #define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 37) > +#define RISCV_HWPROBE_EXT_ZCA (1ULL << 38) > +#define RISCV_HWPROBE_EXT_ZCB (1ULL << 39) > +#define RISCV_HWPROBE_EXT_ZCD (1ULL << 40) > +#define RISCV_HWPROBE_EXT_ZCF (1ULL << 41) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index fc6f4238f0b3..11def345a42d 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -113,6 +113,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZICOND); > EXT_KEY(ZIHINTPAUSE); > EXT_KEY(ZIMOP); > + EXT_KEY(ZCA); > + EXT_KEY(ZCB); > > if (has_vector()) { > EXT_KEY(ZVBB); > @@ -133,6 +135,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZFH); > EXT_KEY(ZFHMIN); > EXT_KEY(ZFA); > + EXT_KEY(ZCD); > + EXT_KEY(ZCF); > } > #undef EXT_KEY > } > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Reviewed-by: Charlie Jenkins