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AJvYcCWA2nahB8I0WgowbufUrCCOAGdUaxrPYcxbmZ0X1T5t5fH/ccl3+EgnjHNcdISE8MEiEvWNcASgVefeM834yOD87J/0CnGXZ1hQ X-Gm-Message-State: AOJu0Ywyt8ncFtMIcs+MqZZ1oWlpW2OENaC7k0iNqxf6TqjkkrRuZRRK 3rwtTc1ynKx79U19eeB3D6i0S3ojWPSBs6mFMtq2AT402/ug9PBdKoVNrpvDqzk= X-Google-Smtp-Source: AGHT+IGkWzxznE9Jlab3s6h48WYrJSCUOQhos16Xu9eqWFR7iZZlKnSnnMYuh0c/JkqvN4t4SCD5ww== X-Received: by 2002:a17:902:e544:b0:1f6:8157:b52f with SMTP id d9443c01a7336-1f6d02c068cmr122398615ad.8.1718040995983; Mon, 10 Jun 2024 10:36:35 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:129d:83bc:830b:8292]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f708e8a6f5sm30483415ad.209.2024.06.10.10.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jun 2024 10:36:35 -0700 (PDT) Date: Mon, 10 Jun 2024 10:36:32 -0700 From: Charlie Jenkins To: Evan Green Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Andy Chiu , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 10/13] riscv: hwprobe: Add thead vendor extension probing Message-ID: References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> <20240609-xtheadvector-v1-10-3fe591d7f109@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Jun 10, 2024 at 09:50:16AM -0700, Evan Green wrote: > On Sun, Jun 9, 2024 at 9:45 PM Charlie Jenkins wrote: > > > > Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which > > allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR > > vendor extension. > > > > This new key will allow userspace code to probe for which thead vendor > > extensions are supported. This API is modeled to be consistent with > > RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit > > corresponding to a supported thead vendor extension of the cpumask set. > > Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program > > to determine all of the supported thead vendor extensions in one call. > > > > Signed-off-by: Charlie Jenkins > > Reviewed-by: Evan Green > > You can continue to keep my tag, but I came up with some nits to pick anyway. > > > --- > > arch/riscv/include/asm/hwprobe.h | 4 +-- > > .../include/asm/vendor_extensions/thead_hwprobe.h | 18 +++++++++++ > > .../include/asm/vendor_extensions/vendor_hwprobe.h | 37 ++++++++++++++++++++++ > > arch/riscv/include/uapi/asm/hwprobe.h | 3 +- > > arch/riscv/include/uapi/asm/vendor/thead.h | 3 ++ > > arch/riscv/kernel/sys_hwprobe.c | 5 +++ > > arch/riscv/kernel/vendor_extensions/Makefile | 1 + > > .../riscv/kernel/vendor_extensions/thead_hwprobe.c | 19 +++++++++++ > > 8 files changed, 87 insertions(+), 3 deletions(-) > > > > diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h > > index 630507dff5ea..e68496b4f8de 100644 > > --- a/arch/riscv/include/asm/hwprobe.h > > +++ b/arch/riscv/include/asm/hwprobe.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > /* > > - * Copyright 2023 Rivos, Inc > > + * Copyright 2023-2024 Rivos, Inc > > */ > > > > #ifndef _ASM_HWPROBE_H > > @@ -8,7 +8,7 @@ > > > > #include > > > > -#define RISCV_HWPROBE_MAX_KEY 6 > > +#define RISCV_HWPROBE_MAX_KEY 7 > > > > static inline bool riscv_hwprobe_key_is_valid(__s64 key) > > { > > diff --git a/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > > new file mode 100644 > > index 000000000000..925fef39a2c0 > > --- /dev/null > > +++ b/arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h > > @@ -0,0 +1,18 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > > +#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H > > + > > +#include > > + > > +#include > > + > > +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD > > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus); > > +#else > > +static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) > > +{ > > + pair->value = 0; > > +} > > +#endif > > + > > +#endif > > diff --git a/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h > > new file mode 100644 > > index 000000000000..b6222e7b519e > > --- /dev/null > > +++ b/arch/riscv/include/asm/vendor_extensions/vendor_hwprobe.h > > @@ -0,0 +1,37 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright 2024 Rivos, Inc > > + */ > > + > > +#ifndef _ASM_RISCV_SYS_HWPROBE_H > > +#define _ASM_RISCV_SYS_HWPROBE_H > > + > > +#include > > + > > +#define EXT_KEY(ext) \ > > Nit: Do you think it should be VENDOR_EXT_KEY? I had a slight ping of > worry that the identifier sounds so generic it might conflict with > something later, but meh maybe it's fine. That's a good point, I will change. > > > > + do { \ > > + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \ > > + pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > > + else \ > > + missing |= RISCV_HWPROBE_VENDOR_EXT_##ext; \ > > + } while (false) > > + > > +/* > > + * Loop through and record extensions that 1) anyone has, and 2) anyone > > + * doesn't have. > > + * > > + * _extension_checks is an arbitrary C block to set the values of pair->value > > + * and missing. It should be filled with EXT_KEY expressions. > > + */ > > +#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_thead_bitmap, _extension_checks) \ > > Nit: This macro was meant to be generic for all vendors, but you've > named one of the parameters per_hart_thead_bitmap. :) Whoops, thank you! - Charlie > > > + do { \ > > + int cpu; \ > > + u64 missing; \ > > + for_each_cpu(cpu, (cpus)) { \ > > + struct riscv_isavendorinfo *isainfo = &(per_hart_thead_bitmap)[cpu]; \ > > + _extension_checks \ > > + } \ > > + (pair)->value &= ~missing; \ > > + } while (false) \ > > + > > +#endif /* _ASM_RISCV_SYS_HWPROBE_H */ > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index dda76a05420b..155a83dd1cdf 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > /* > > - * Copyright 2023 Rivos, Inc > > + * Copyright 2023-2024 Rivos, Inc > > */ > > > > #ifndef _UAPI_ASM_HWPROBE_H > > @@ -68,6 +68,7 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) > > #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) > > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > > +#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 7 > > /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ > > > > /* Flags */ > > diff --git a/arch/riscv/include/uapi/asm/vendor/thead.h b/arch/riscv/include/uapi/asm/vendor/thead.h > > new file mode 100644 > > index 000000000000..43790ebe5faf > > --- /dev/null > > +++ b/arch/riscv/include/uapi/asm/vendor/thead.h > > @@ -0,0 +1,3 @@ > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > + > > +#define RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR (1 << 0) > > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > > index 969ef3d59dbe..e39fa70083d3 100644 > > --- a/arch/riscv/kernel/sys_hwprobe.c > > +++ b/arch/riscv/kernel/sys_hwprobe.c > > @@ -13,6 +13,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > > > @@ -217,6 +218,10 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, > > pair->value = riscv_cboz_block_size; > > break; > > > > + case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0: > > + hwprobe_isa_vendor_ext_thead_0(pair, cpus); > > + break; > > + > > /* > > * For forward compatibility, unknown keys don't fail the whole > > * call, but get their element key set to -1 and value set to 0 > > diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile > > index 353522cb3bf0..866414c81a9f 100644 > > --- a/arch/riscv/kernel/vendor_extensions/Makefile > > +++ b/arch/riscv/kernel/vendor_extensions/Makefile > > @@ -2,3 +2,4 @@ > > > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o > > obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o > > +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead_hwprobe.o > > diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > > new file mode 100644 > > index 000000000000..53f65942f7e8 > > --- /dev/null > > +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > > @@ -0,0 +1,19 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > + > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > + > > +#include > > +#include > > + > > +void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus) > > +{ > > + VENDOR_EXTENSION_SUPPORTED(pair, cpus, > > + riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { > > + EXT_KEY(XTHEADVECTOR); > > + }); > > +} > > > > -- > > 2.44.0 > >