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AJvYcCWW6aH4X8uC2+oXbF3KsT+VXBiKLLqFWiee4iVC0q4VAXwyHcLS6Ky+Ob1EUnhLv0WplmBuxnFwnQJb/hFXiY80mSVVWs91vjFU X-Gm-Message-State: AOJu0YzeqjsjsE2ZufsLV8NxPgt5cXcQofzCIDMDFWjiXF7tCDCT9g90 mVKR+tjmWzt5vwTIKMg5MvWbB1PcLANKZPoccpMTrpnpxpJgHOyGfMQ2/fmaaKU= X-Google-Smtp-Source: AGHT+IGI7ZtC5yMFeVhgobcpC4ELjQ0rXq8graZvm2aNnJqlgdJJt9Tf50Z+1bVL5t64KhWiB1DChw== X-Received: by 2002:a17:902:cf04:b0:1f6:f5bc:51c5 with SMTP id d9443c01a7336-1f6f5bc5391mr72332595ad.47.1718041886043; Mon, 10 Jun 2024 10:51:26 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:129d:83bc:830b:8292]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f70eeaedf7sm27441255ad.84.2024.06.10.10.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jun 2024 10:51:25 -0700 (PDT) Date: Mon, 10 Jun 2024 10:51:23 -0700 From: Charlie Jenkins To: Jessica Clarke Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Jonathan Corbet , Shuah Khan , Guo Ren , Evan Green , Andy Chiu , linux-riscv , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Message-ID: References: <20240609-xtheadvector-v1-0-3fe591d7f109@rivosinc.com> <20240609-xtheadvector-v1-3-3fe591d7f109@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Jun 10, 2024 at 06:49:30PM +0100, Jessica Clarke wrote: > On 10 Jun 2024, at 05:45, Charlie Jenkins wrote: > > > > The D1/D1s SoCs support xtheadvector so it can be included in the > > devicetree. Also include vlenb for the cpu. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > index 64c3c2e6cbe0..50c9f4ec8a7f 100644 > > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > > riscv,isa = "rv64imafdc"; > > riscv,isa-base = "rv64i"; > > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > - "zifencei", "zihpm"; > > + "zifencei", "zihpm", "xtheadvector"; > > + riscv,vlenb = <128>; > > thread,vlenb Oh right, thank you! - Charlie > > Jess > > > #cooling-cells = <2>; > > > > cpu0_intc: interrupt-controller { > > > > -- > > 2.44.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >