From: Charlie Jenkins <charlie@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
Andy Chiu <andy.chiu@sifive.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 02/13] dt-bindings: thead: add a vlen register length property
Date: Mon, 10 Jun 2024 09:38:06 -0700 [thread overview]
Message-ID: <Zmcr7pP+XEWHYTsy@ghost> (raw)
In-Reply-To: <20240610-unaltered-crazily-5b63e224d633@spud>
On Mon, Jun 10, 2024 at 05:29:23PM +0100, Conor Dooley wrote:
> On Sun, Jun 09, 2024 at 09:45:07PM -0700, Charlie Jenkins wrote:
> > Add a property analogous to the vlenb CSR so that software can detect
> > the vector length of each CPU prior to it being brought online.
> > Currently software has to assume that the vector length read from the
> > boot CPU applies to all possible CPUs. On T-Head CPUs implementing
> > pre-ratification vector, reading the th.vlenb CSR may produce an illegal
> > instruction trap, so this property is required on such systems.
> >
> > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> > ---
> > Documentation/devicetree/bindings/riscv/thead.yaml | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml
> > index 301912dcd290..5e578df36ac5 100644
> > --- a/Documentation/devicetree/bindings/riscv/thead.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/thead.yaml
> > @@ -28,6 +28,13 @@ properties:
> > - const: sipeed,lichee-module-4a
> > - const: thead,th1520
> >
> > +thead,vlenb:
>
> This needs to move back into cpus.yaml, this file documents root node
> compatibles (boards and socs etc) and is not for CPUs. If you want to
> restrict this to T-Head CPUs only, it must be done in cpus.yaml with
> a conditional `if: not: ... then: properties: thead,vlenb: false`.
>
> Please test your bindings.
Now that I know `make dt_binding_check` exists I will use that in the
future!
- Charlie
>
> Thanks,
> Conor.
>
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description:
> > + VLEN/8, the vector register length in bytes. This property is required in
> > + systems where the vector register length is not identical on all harts, or
> > + the vlenb CSR is not available.
> > +
> > additionalProperties: true
> >
> > ...
> >
> > --
> > 2.44.0
> >
next prev parent reply other threads:[~2024-06-10 16:38 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-10 4:45 [PATCH 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-06-10 4:45 ` [PATCH 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-06-11 12:06 ` Guo Ren
2024-06-11 17:51 ` Charlie Jenkins
2024-06-10 4:45 ` [PATCH 02/13] dt-bindings: thead: add a vlen register length property Charlie Jenkins
2024-06-10 6:27 ` Rob Herring (Arm)
2024-06-10 16:29 ` Conor Dooley
2024-06-10 16:38 ` Charlie Jenkins [this message]
2024-06-10 19:28 ` Conor Dooley
2024-06-10 4:45 ` [PATCH 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-06-10 17:49 ` Jessica Clarke
2024-06-10 17:51 ` Charlie Jenkins
2024-06-10 4:45 ` [PATCH 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-06-10 4:45 ` [PATCH 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-06-10 17:51 ` Jessica Clarke
2024-06-10 18:10 ` Charlie Jenkins
2024-06-10 4:45 ` [PATCH 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-06-10 4:45 ` [PATCH 07/13] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-06-10 4:45 ` [PATCH 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-06-10 4:45 ` [PATCH 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-06-10 4:45 ` [PATCH 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-06-10 16:50 ` Evan Green
2024-06-10 17:36 ` Charlie Jenkins
2024-06-10 4:45 ` [PATCH 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-06-10 4:45 ` [PATCH 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-06-10 4:45 ` [PATCH 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
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