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Thu, 27 Jun 2024 06:45:54 -0700 (PDT) Received: from andrea ([217.201.220.159]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-584d1280e93sm902182a12.33.2024.06.27.06.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jun 2024 06:45:54 -0700 (PDT) Date: Thu, 27 Jun 2024 15:45:47 +0200 From: Andrea Parri To: Alexandre Ghiti Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Nathan Chancellor , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v2 06/10] riscv: Implement xchg8/16() using Zabha Message-ID: References: <20240626130347.520750-1-alexghiti@rivosinc.com> <20240626130347.520750-7-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240626130347.520750-7-alexghiti@rivosinc.com> > -#define __arch_xchg_masked(sc_sfx, prepend, append, r, p, n) \ > +#define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append, \ > + swap_append, r, p, n) \ > ({ \ > + __label__ zabha, end; \ > + \ > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \ > + asm goto(ALTERNATIVE("nop", "j %[zabha]", 0, \ > + RISCV_ISA_EXT_ZABHA, 1) \ > + : : : : zabha); \ > + } \ > + \ > u32 *__ptr32b = (u32 *)((ulong)(p) & ~0x3); \ > ulong __s = ((ulong)(p) & (0x4 - sizeof(*p))) * BITS_PER_BYTE; \ > ulong __mask = GENMASK(((sizeof(*p)) * BITS_PER_BYTE) - 1, 0) \ > @@ -28,12 +37,25 @@ > " or %1, %1, %z3\n" \ > " sc.w" sc_sfx " %1, %1, %2\n" \ > " bnez %1, 0b\n" \ > - append \ > + sc_append \ > : "=&r" (__retx), "=&r" (__rc), "+A" (*(__ptr32b)) \ > : "rJ" (__newx), "rJ" (~__mask) \ > : "memory"); \ > \ > r = (__typeof__(*(p)))((__retx & __mask) >> __s); \ > + goto end; \ > + \ > +zabha: \ > + if (IS_ENABLED(CONFIG_RISCV_ISA_ZABHA)) { \ > + __asm__ __volatile__ ( \ > + prepend \ > + " amoswap" swap_sfx " %0, %z2, %1\n" \ > + swap_append \ > + : "=&r" (r), "+A" (*(p)) \ > + : "rJ" (n) \ > + : "memory"); \ > + } \ > +end:; \ > }) As for patch #1: why the semicolon? and should the second IS_ENABLED() be kept? > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index e17d0078a651..f71ddd2ca163 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -81,6 +81,7 @@ > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 > #define RISCV_ISA_EXT_XANDESPMU 74 > +#define RISCV_ISA_EXT_ZABHA 75 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 5ef48cb20ee1..c125d82c894b 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -257,6 +257,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > + __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA), > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), To be squashed into patch #3? Andrea