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From: Charlie Jenkins <charlie@rivosinc.com>
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Conor Dooley" <conor@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Clément Léger" <cleger@rivosinc.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Xiao Wang" <xiao.w.wang@intel.com>,
	"Andy Chiu" <andy.chiu@sifive.com>,
	"Eric Biggers" <ebiggers@google.com>,
	"Greentime Hu" <greentime.hu@sifive.com>,
	"Björn Töpel" <bjorn@rivosinc.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Costa Shulyupin" <costa.shul@redhat.com>,
	"Andrew Morton" <akpm@linux-foundation.org>,
	"Baoquan He" <bhe@redhat.com>,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Zong Li" <zong.li@sifive.com>,
	"Sami Tolvanen" <samitolvanen@google.com>,
	"Ben Dooks" <ben.dooks@codethink.co.uk>,
	"Alexandre Ghiti" <alexghiti@rivosinc.com>,
	"Gustavo A. R. Silva" <gustavoars@kernel.org>,
	"Erick Archer" <erick.archer@gmx.com>,
	"Joel Granados" <j.granados@samsung.com>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH v4 7/7] RISC-V: hwprobe: Document unaligned vector perf key
Date: Thu, 11 Jul 2024 15:23:11 -0700	[thread overview]
Message-ID: <ZpBbT1OquCCwUTWA@ghost> (raw)
In-Reply-To: <20240711215846.834365-8-jesse@rivosinc.com>

On Thu, Jul 11, 2024 at 05:58:46PM -0400, Jesse Taube wrote:
> Document key for reporting the speed of unaligned vector accesses.
> The descriptions are the same as the scalar equivalent values.
> 
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> V1 -> V2:
>   - New patch
> V2 -> V3:
>  - Specify access width
> V3 -> V4:
>  - Clarify we're talking about byte accesses using vector registers
>  - Spell out _VECTOR_ in macros
> ---
>  Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 78acd37b6477..f83a13dc4cbc 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -238,3 +238,19 @@ The following keys are defined:
>  
>  * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
>    represents the size of the Zicboz block in bytes.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_VECTOR_MISALIGNED_PERF`: An enum value describing the
> +     performance of misaligned vector accesses on the selected set of processors.
> +
> +  * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN`: The performance of misaligned
> +    vector accesses is unknown.
> +
> +  * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_SLOW`: 32-bit misaligned accesses using vector
> +    registers are slower than the equivalent quantity of byte accesses via vector registers.
> +    Misaligned accesses may be supported directly in hardware, or trapped and emulated by software.
> +
> +  * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_FAST`: 32-bit misaligned accesses using vector
> +    registers are faster than the equivalent quantity of byte accesses via vector registers.
> +
> +  * :c:macro:`RISCV_HWPROBE_VECTOR_MISALIGNED_UNSUPPORTED`: Misaligned vector accesses are
> +    not supported at all and will generate a misaligned address fault.
> -- 
> 2.45.2
> 

Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>


  reply	other threads:[~2024-07-11 22:23 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-11 21:58 [PATCH v4 0/7] RISC-V: Detect and report speed of unaligned vector accesses Jesse Taube
2024-07-11 21:58 ` [PATCH v4 1/7] RISC-V: Add Zicclsm to cpufeature and hwprobe Jesse Taube
2024-07-11 21:58 ` [PATCH v4 2/7] dt-bindings: riscv: Add Zicclsm ISA extension description Jesse Taube
2024-07-11 21:58 ` [PATCH v4 3/7] RISC-V: Check scalar unaligned access on all CPUs Jesse Taube
2024-07-11 22:38   ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 4/7] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED Jesse Taube
2024-07-11 22:39   ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 5/7] RISC-V: Detect unaligned vector accesses supported Jesse Taube
2024-07-11 22:46   ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 6/7] RISC-V: Report vector unaligned access speed hwprobe Jesse Taube
2024-07-11 22:48   ` Charlie Jenkins
2024-07-11 21:58 ` [PATCH v4 7/7] RISC-V: hwprobe: Document unaligned vector perf key Jesse Taube
2024-07-11 22:23   ` Charlie Jenkins [this message]
2024-07-11 22:32 ` [PATCH v4 0/7] RISC-V: Detect and report speed of unaligned vector accesses Charlie Jenkins

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