From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AF1A17C7C9; Thu, 22 Aug 2024 15:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724341461; cv=none; b=QgOtT3Ixp3X9Qzi+PQLKmgnV9oOiL2gu3pqiZqOWje8igZKaLAMpOYNxJ5D9BfIvIWQhkE8SxpqjGpPlRzL3i0XwEMO1CWpL0esqone5Eh50EPwvKTODtURoj+Z0ULceeSnN9MslH/w8eDqPU2kVfS8zsNNxw0zPua1v7YjM+c8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724341461; c=relaxed/simple; bh=ZOEMpQPu9K+XfBr85CGnu17+4EMpvj/m9mXtvb+H1ug=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=C3xfbOgB0hUARROc8LCF+utku2OhFR2EVIYlePCmRjNNodvGsWOhJDYE8Gvl2zzTtomKtAva++H8A7TLDWc3a5tIKzkLu3a9imYrgjkjAOygXSrR/8fm32KKXmx7GHxtW9Z2MxMSf2GUlwtCElQ8Ism/oonBMmE2XQ1O8RYvWpo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id DDAD5C32782; Thu, 22 Aug 2024 15:44:14 +0000 (UTC) Date: Thu, 22 Aug 2024 16:44:12 +0100 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy , Kees Cook , "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , Thiago Jung Bauermann , Ross Burton , Yury Khrustalev , Wilco Dijkstra , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v11 18/39] arm64/traps: Handle GCS exceptions Message-ID: References: <20240822-arm64-gcs-v11-0-41b81947ecb5@kernel.org> <20240822-arm64-gcs-v11-18-41b81947ecb5@kernel.org> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240822-arm64-gcs-v11-18-41b81947ecb5@kernel.org> On Thu, Aug 22, 2024 at 02:15:21AM +0100, Mark Brown wrote: > +static void noinstr el0_gcs(struct pt_regs *regs, unsigned long esr) > +{ > + enter_from_user_mode(regs); > + local_daif_restore(DAIF_PROCCTX); > + do_el0_gcs(regs, esr); > + exit_to_user_mode(regs); > +} > + > static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr) > { > enter_from_user_mode(regs); > @@ -766,6 +786,9 @@ asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) > case ESR_ELx_EC_MOPS: > el0_mops(regs, esr); > break; > + case ESR_ELx_EC_GCS: > + el0_gcs(regs, esr); > + break; > case ESR_ELx_EC_BREAKPT_LOW: > case ESR_ELx_EC_SOFTSTP_LOW: > case ESR_ELx_EC_WATCHPT_LOW: > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 9e22683aa921..d410dcc12ed8 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -500,6 +500,16 @@ void do_el1_bti(struct pt_regs *regs, unsigned long esr) > die("Oops - BTI", regs, esr); > } > > +void do_el0_gcs(struct pt_regs *regs, unsigned long esr) > +{ > + force_signal_inject(SIGSEGV, SEGV_CPERR, regs->pc, 0); > +} Just double checking: a GCSPOPM (for example, it can be a RET) from a non-GCS page would generate a classic permission fault with ISS2.GCS set rather than a GCS exception. That's my reading from the Arm ARM pseudocode, the text isn't clear to me. -- Catalin