Re: [PATCH v3 04/14] x86/msr-index: define AMD heterogeneous CPU related MSR

["Gautham R. Shenoy" <gautham.shenoy@amd.com>]

On Tue, Oct 15, 2024 at 04:36:35PM -0500, Mario Limonciello wrote:
> From: Perry Yuan <perry.yuan@amd.com>
> 
> Introduces new MSR registers for AMD hardware feedback support.
> These registers enable the system to provide workload classification
> and configuration capabilities.
> 
> Signed-off-by: Perry Yuan <perry.yuan@amd.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>

> ---
>  arch/x86/include/asm/msr-index.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 3ae84c3b8e6d..0cd5ffe50f4a 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -712,6 +712,11 @@
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
>  #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
>  
> +/* AMD Hardware Feedback Support MSRs */
> +#define AMD_WORKLOAD_CLASS_CONFIG      0xc0000500
> +#define AMD_WORKLOAD_CLASS_ID          0xc0000501
> +#define AMD_WORKLOAD_HRST              0xc0000502
> +
>  /* AMD Last Branch Record MSRs */
>  #define MSR_AMD64_LBR_SELECT			0xc000010e
>  
> -- 
> 2.43.0
>