From: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
To: Conor Dooley <conor@kernel.org>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, anup@brainfault.org,
pbonzini@redhat.com, shuah@kernel.org, cyan.yang@sifive.com,
cleger@rivosinc.com, charlie@rivosinc.com,
cuiyunhui@bytedance.com, samuel.holland@sifive.com,
namcao@linutronix.de, jesse@rivosinc.com, inochiama@gmail.com,
yongxuan.wang@sifive.com, ajones@ventanamicro.com,
parri.andrea@gmail.com, mikisabate@gmail.com,
yikming2222@gmail.com, thomas.weissschuh@linutronix.de,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions
Date: Mon, 25 Aug 2025 23:26:13 +0800 [thread overview]
Message-ID: <a2cc4cbe-82ca-4a89-b623-73721a1f3baf@isrc.iscas.ac.cn> (raw)
In-Reply-To: <20250822-purge-doubling-f38988284db1@spud>
On 2025/8/23 0:33, Conor Dooley wrote:
> On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
>> Add descriptions for the Zilsd (Load/Store pair instructions) and
>> Zclsd (Compressed Load/Store pair instructions) ISA extensions
>> which were ratified in commit f88abf1 ("Integrating load/store
>> pair for RV32 with the main manual") of the riscv-isa-manual.
>>
>> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
>> ---
>> .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> index ede6a58ccf53..d72ffe8f6fa7 100644
>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
>> @@ -366,6 +366,20 @@ properties:
>> guarantee on LR/SC sequences, as ratified in commit b1d806605f87
>> ("Updated to ratified state.") of the riscv profiles specification.
>>
>> + - const: zilsd
>> + description:
>> + The standard Zilsd extension which provides support for aligned
>> + register-pair load and store operations in 32-bit instruction
>> + encodings, as ratified in commit f88abf1 ("Integrating
>> + load/store pair for RV32 with the main manual") of riscv-isa-manual.
>> +
>> + - const: zclsd
>> + description:
>> + The Zclsd extension implements the compressed (16-bit) version of the
>> + Load/Store Pair for RV32. As with Zilsd, this extension was ratified
>> + in commit f88abf1 ("Integrating load/store pair for RV32 with the
>> + main manual") of riscv-isa-manual.
>> +
>> - const: zk
>> description:
>> The standard Zk Standard Scalar cryptography extension as ratified
>> @@ -847,6 +861,16 @@ properties:
>> anyOf:
>> - const: v
>> - const: zve32x
>> + # Zclsd depends on Zilsd and Zca
>> + - if:
>> + contains:
>> + anyOf:
>> + - const: zclsd
>> + then:
>> + contains:
>> + anyOf:
>> + - const: zilsd
>> + - const: zca
>>
>> allOf:
>> # Zcf extension does not exist on rv64
>> @@ -864,6 +888,21 @@ allOf:
>> not:
>> contains:
>> const: zcf
>> + # Zilsd extension does not exist on rv64
>> + - if:
>> + properties:
>
>> + riscv,isa-extensions:
>> + contains:
>> + const: zilsd
>
> This syntax is odd, it shouldn't be required to have zilsd in here and
> in the then. Did you copy this from Zcf or come up with it yourself
> because it didn't work otherwise?
>
Yes, I did model this after the existing Zcf constraint in the same
file. The structure is nearly identical: cheking for presence of the
extension and rv64i, then forbidding it in the "then" branch.
I've tested confirmed that removing the "contains: const: zilsd" from
the "if" condition still correctly enforces that zilsd must not appear
when rv64i is present. The "then" clause with "not: contains" is sufficient.
Given that the validation behavior is equivalent, but the logic is
cleaner and less redundant without the extra "contains", would you
recommend updating it to the simpler form:
- if:
properties:
riscv,isa-base:
contains:
const: rv64i
then:
properties:
riscv,isa-extensions:
not:
contains:
const: zilsd
If so, I'll update it in the next revision.
Thanks for the review!
Best regards,
Pincheng Wang
>> + riscv,isa-base:
>> + contains:
>> + const: rv64i
>> + then:
>> + properties:
>> + riscv,isa-extensions:
>> + not:
>> + contains:
>> + const: zilsd
>>
>> additionalProperties: true
>> ...
>> --
>> 2.39.5
>>
next prev parent reply other threads:[~2025-08-25 15:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-21 14:01 [PATCH v1 RESEND 0/5] RISC-V: Add Zilsd/Zclsd support in hwprobe and KVM Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions Pincheng Wang
2025-08-22 16:33 ` Conor Dooley
2025-08-25 15:26 ` Pincheng Wang [this message]
2025-08-25 16:23 ` Conor Dooley
2025-08-22 22:34 ` Inochi Amaoto
2025-08-25 16:19 ` Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 2/5] riscv: add ISA extension parsing for Zilsd and Zclsd Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 3/5] riscv: hwprobe: export Zilsd and Zclsd ISA extensions Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 4/5] riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM Pincheng Wang
2025-08-21 14:01 ` [PATCH v1 RESEND 5/5] KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list test Pincheng Wang
-- strict thread matches above, loose matches on Subject: below --
2025-08-25 14:58 [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions pincheng.plct
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