From: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
To: "Mehta, Sohil" <sohil.mehta@intel.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
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"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>
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"ardb@kernel.org" <ardb@kernel.org>,
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Subject: Re: [PATCH v10 08/15] x86/vsyscall: Reorganize the page fault emulation code
Date: Tue, 7 Oct 2025 18:37:27 +0000 [thread overview]
Message-ID: <a33d59c7add98dd9ef352ac95178821dbcd0ce0e.camel@intel.com> (raw)
In-Reply-To: <20251007065119.148605-9-sohil.mehta@intel.com>
On Mon, 2025-10-06 at 23:51 -0700, Sohil Mehta wrote:
> Separate out the actual vsyscall emulation from the #PF specific
> handling in preparation for the upcoming #GP emulation.
>
> No functional change intended.
>
> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
> Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
> ---
> v10:
> - Modify the code flow slightly to make it easier to follow.
> ---
> arch/x86/entry/vsyscall/vsyscall_64.c | 63 ++++++++++++++-------------
> arch/x86/include/asm/vsyscall.h | 7 ++-
> arch/x86/mm/fault.c | 2 +-
> 3 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/arch/x86/entry/vsyscall/vsyscall_64.c b/arch/x86/entry/vsyscall/vsyscall_64.c
> index 6e6c0a740837..4c3f49bf39e6 100644
> --- a/arch/x86/entry/vsyscall/vsyscall_64.c
> +++ b/arch/x86/entry/vsyscall/vsyscall_64.c
> @@ -112,43 +112,13 @@ static bool write_ok_or_segv(unsigned long ptr, size_t size)
> }
> }
>
> -bool emulate_vsyscall(unsigned long error_code,
> - struct pt_regs *regs, unsigned long address)
> +static bool __emulate_vsyscall(struct pt_regs *regs, unsigned long address)
> {
> unsigned long caller;
> int vsyscall_nr, syscall_nr, tmp;
> long ret;
> unsigned long orig_dx;
>
> - /* Write faults or kernel-privilege faults never get fixed up. */
> - if ((error_code & (X86_PF_WRITE | X86_PF_USER)) != X86_PF_USER)
> - return false;
> -
> - /*
> - * Assume that faults at regs->ip are because of an
> - * instruction fetch. Return early and avoid
> - * emulation for faults during data accesses:
> - */
> - if (address != regs->ip) {
> - /* Failed vsyscall read */
> - if (vsyscall_mode == EMULATE)
> - return false;
> -
> - /*
> - * User code tried and failed to read the vsyscall page.
> - */
> - warn_bad_vsyscall(KERN_INFO, regs, "vsyscall read attempt denied -- look up the vsyscall kernel parameter if you need a workaround");
> - return false;
> - }
> -
> - /*
> - * X86_PF_INSTR is only set when NX is supported. When
> - * available, use it to double-check that the emulation code
> - * is only being used for instruction fetches:
> - */
> - if (cpu_feature_enabled(X86_FEATURE_NX))
> - WARN_ON_ONCE(!(error_code & X86_PF_INSTR));
> -
> /*
> * No point in checking CS -- the only way to get here is a user mode
> * trap to a high address, which means that we're in 64-bit user code.
I don't know. Is this as true any more? We are now sometimes guessing based on
regs->ip of a #GP. What if the kernel accidentally tries to jump to the vsyscall
address? Then we are reading the kernel stack and strange things. Maybe it's
worth replacing the comment with a check? Feel free to call this paranoid.
> @@ -281,6 +251,37 @@ bool emulate_vsyscall(unsigned long error_code,
> return true;
> }
>
> +bool emulate_vsyscall_pf(unsigned long error_code, struct pt_regs *regs,
> + unsigned long address)
> +{
> + /* Write faults or kernel-privilege faults never get fixed up. */
> + if ((error_code & (X86_PF_WRITE | X86_PF_USER)) != X86_PF_USER)
> + return false;
> +
> + /*
> + * Assume that faults at regs->ip are because of an instruction
> + * fetch. Return early and avoid emulation for faults during
> + * data accesses:
> + */
> + if (address != regs->ip) {
> + /* User code tried and failed to read the vsyscall page. */
> + if (vsyscall_mode != EMULATE)
> + warn_bad_vsyscall(KERN_INFO, regs, "vsyscall read attempt denied -- look up the vsyscall kernel parameter if you need a workaround");
> +
> + return false;
> + }
> +
> + /*
> + * X86_PF_INSTR is only set when NX is supported. When
> + * available, use it to double-check that the emulation code
> + * is only being used for instruction fetches:
> + */
> + if (cpu_feature_enabled(X86_FEATURE_NX))
> + WARN_ON_ONCE(!(error_code & X86_PF_INSTR));
> +
> + return __emulate_vsyscall(regs, address);
> +}
> +
> /*
> * A pseudo VMA to allow ptrace access for the vsyscall page. This only
> * covers the 64bit vsyscall page now. 32bit has a real VMA now and does
> diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
> index 472f0263dbc6..f34902364972 100644
> --- a/arch/x86/include/asm/vsyscall.h
> +++ b/arch/x86/include/asm/vsyscall.h
> @@ -14,12 +14,11 @@ extern void set_vsyscall_pgtable_user_bits(pgd_t *root);
> * Called on instruction fetch fault in vsyscall page.
> * Returns true if handled.
> */
> -extern bool emulate_vsyscall(unsigned long error_code,
> - struct pt_regs *regs, unsigned long address);
> +bool emulate_vsyscall_pf(unsigned long error_code, struct pt_regs *regs, unsigned long address);
> #else
> static inline void map_vsyscall(void) {}
> -static inline bool emulate_vsyscall(unsigned long error_code,
> - struct pt_regs *regs, unsigned long address)
> +static inline bool emulate_vsyscall_pf(unsigned long error_code,
> + struct pt_regs *regs, unsigned long address)
> {
> return false;
> }
> diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
> index 998bd807fc7b..fbcc2da75fd6 100644
> --- a/arch/x86/mm/fault.c
> +++ b/arch/x86/mm/fault.c
> @@ -1316,7 +1316,7 @@ void do_user_addr_fault(struct pt_regs *regs,
> * to consider the PF_PK bit.
> */
> if (is_vsyscall_vaddr(address)) {
> - if (emulate_vsyscall(error_code, regs, address))
> + if (emulate_vsyscall_pf(error_code, regs, address))
> return;
> }
> #endif
next prev parent reply other threads:[~2025-10-07 18:37 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-07 6:51 [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 01/15] x86/cpu: Enumerate the LASS feature bits Sohil Mehta
2025-10-07 18:19 ` Edgecombe, Rick P
2025-10-07 18:28 ` Dave Hansen
2025-10-07 20:20 ` Sohil Mehta
2025-10-07 20:38 ` Edgecombe, Rick P
2025-10-07 20:53 ` Sohil Mehta
2025-10-16 3:10 ` H. Peter Anvin
2025-10-07 20:49 ` Sohil Mehta
2025-10-07 23:16 ` Xin Li
2025-10-08 16:00 ` Edgecombe, Rick P
2025-10-16 15:35 ` Borislav Petkov
2025-10-21 18:03 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 02/15] x86/asm: Introduce inline memcpy and memset Sohil Mehta
2025-10-21 12:47 ` Borislav Petkov
2025-10-21 13:48 ` David Laight
2025-10-21 18:06 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 03/15] x86/alternatives: Disable LASS when patching kernel alternatives Sohil Mehta
2025-10-07 16:55 ` Edgecombe, Rick P
2025-10-07 22:28 ` Sohil Mehta
2025-10-08 16:22 ` Edgecombe, Rick P
2025-10-10 17:10 ` Sohil Mehta
2025-10-21 20:03 ` Borislav Petkov
2025-10-21 20:55 ` Sohil Mehta
2025-10-22 9:56 ` Borislav Petkov
2025-10-22 19:49 ` Sohil Mehta
2025-10-22 20:03 ` Luck, Tony
2025-10-22 8:25 ` Peter Zijlstra
2025-10-22 9:40 ` Borislav Petkov
2025-10-22 10:22 ` Peter Zijlstra
2025-10-22 10:52 ` Borislav Petkov
2025-10-07 6:51 ` [PATCH v10 04/15] x86/cpu: Set LASS CR4 bit as pinning sensitive Sohil Mehta
2025-10-07 18:24 ` Edgecombe, Rick P
2025-10-07 23:11 ` Sohil Mehta
2025-10-08 16:52 ` Edgecombe, Rick P
2025-10-10 19:03 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 05/15] x86/cpu: Defer CR pinning enforcement until late_initcall() Sohil Mehta
2025-10-07 17:23 ` Edgecombe, Rick P
2025-10-07 23:05 ` Sohil Mehta
2025-10-08 17:36 ` Edgecombe, Rick P
2025-10-10 20:45 ` Sohil Mehta
2025-10-15 21:17 ` Sohil Mehta
2025-10-17 19:28 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 06/15] x86/efi: Disable LASS while mapping the EFI runtime services Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 07/15] x86/kexec: Disable LASS during relocate kernel Sohil Mehta
2025-10-07 17:43 ` Edgecombe, Rick P
2025-10-07 22:33 ` Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 08/15] x86/vsyscall: Reorganize the page fault emulation code Sohil Mehta
2025-10-07 18:37 ` Edgecombe, Rick P [this message]
2025-10-07 18:48 ` Dave Hansen
2025-10-07 19:53 ` Edgecombe, Rick P
2025-10-07 22:52 ` Sohil Mehta
2025-10-08 17:42 ` Edgecombe, Rick P
2025-10-30 16:58 ` Andy Lutomirski
2025-10-30 17:22 ` H. Peter Anvin
2025-10-30 17:35 ` Andy Lutomirski
2025-10-30 19:28 ` Sohil Mehta
2025-10-30 21:37 ` David Laight
2025-10-07 6:51 ` [PATCH v10 09/15] x86/traps: Consolidate user fixups in exc_general_protection() Sohil Mehta
2025-10-07 17:46 ` Edgecombe, Rick P
2025-10-07 22:41 ` Sohil Mehta
2025-10-08 17:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 10/15] x86/vsyscall: Add vsyscall emulation for #GP Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 11/15] x86/vsyscall: Disable LASS if vsyscall mode is set to EMULATE Sohil Mehta
2025-10-07 18:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 12/15] x86/traps: Communicate a LASS violation in #GP message Sohil Mehta
2025-10-07 18:07 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 13/15] x86/traps: Generalize #GP address decode and hint code Sohil Mehta
2025-10-07 18:43 ` Edgecombe, Rick P
2025-10-07 6:51 ` [PATCH v10 14/15] x86/traps: Provide additional hints for a kernel stack segment fault Sohil Mehta
2025-10-07 6:51 ` [PATCH v10 15/15] x86/cpu: Enable LASS by default during CPU initialization Sohil Mehta
2025-10-07 18:42 ` Edgecombe, Rick P
2025-10-07 16:23 ` [PATCH v10 00/15] x86: Enable Linear Address Space Separation support Edgecombe, Rick P
2025-10-17 19:52 ` Sohil Mehta
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