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Fri, 25 Apr 2025 22:59:37 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 22/22] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Date: Fri, 25 Apr 2025 22:58:17 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|BY5PR12MB4179:EE_ X-MS-Office365-Filtering-Correlation-Id: 6e173b3d-b6a0-4717-554c-08dd848790cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?iwjwrvfNHInnhQkW/Rd/Ag2MN0MhyMPJaNkRnoWCZTL4QY08oDBYpABgwR58?= =?us-ascii?Q?GPM6yxpIRTCYKJU8rFYM6JFN8vCkas4lnOgGiliaCtC6R2pLMc+WmUd3cO6h?= =?us-ascii?Q?xefZETqzYyKqwY34PQybRgn8aMCI1lU/nsPf87zXpR69aK7HaEGOWAe+dUsh?= =?us-ascii?Q?ALr5ZGxhB8ZHSx4ltoNQPPrAscrII7dYcaJd+HofndUn7v+tdOgeIOoaBRhA?= =?us-ascii?Q?+x20YhG00cWyJf3Vy8xcMMFV7XMLq0ujAysSrlzhC6+1c3/mezXnLN4wCiEl?= =?us-ascii?Q?0MiQZLQDNGwFZXzrwumelsd70Zi6546FHblkmq3IjflraE4bWT1V2w4Ux2Zz?= =?us-ascii?Q?aW+ksaktDdgnqfBtNDOzHO960deflAidqWUs9Za/nJe3lOSkPX6LxH6dg2jw?= =?us-ascii?Q?n+ZvSpnEPpmAWWaqUxvZdIZ8ZWDax5mQdgqRnyRAVVmhMthKxKb7NLFs7T/1?= =?us-ascii?Q?e/tnbVnJpN62e7V3R5kCWHY9oyyajmQUUNVAE8JgTzrlwtt5c4Dvgynotuyx?= =?us-ascii?Q?+HI/bNSpsEw7beNLF3fcd4KJCLZ49HPB0E/WEnPZwJKFn86GYiq2udKODOZ0?= =?us-ascii?Q?9xhOy7hlrmOq7CqxAVD8vFCRwOsvhyohat6NtmNSsliNJio5OEpBprm1+yVv?= =?us-ascii?Q?XUH2LcMigyRTT1y31s+4bV1+zIPMl/NtYaX7pLFH+rPr530TJ0WdecLetImy?= =?us-ascii?Q?+0tLJewW7ow4LEvXrezsGl7urd0xRLobvIwkNAoDNqLt7vEJ4sdOpDuqm7XD?= =?us-ascii?Q?7PHu3zwC/iEu8PnyFk43Twq8TID8TYh2i0C/QOUh/KuYjnlGLIVIVbQnYbP3?= =?us-ascii?Q?Z8tYgV9eAjvEWZ/un6kxERAC9YrZP6kSU8M0wdbkun2tQ4ty8VvNMYp4qnYx?= =?us-ascii?Q?2RhDMaCUzdFT86x/wwFas9aPVDJ/847gatc+Wot294VcvCZr72mkuDPF2fIJ?= =?us-ascii?Q?g38n+jJYh0hXmb0Rok9mB8u4eh3eN3v8BABYOkLjUQVac5OgpSwBpG9XCE+4?= =?us-ascii?Q?NslAjMWKBSqi1DLNRbeNLZfrtwe1b7AnCEN6JKP6X6wMG0ihMrt7PZFF8U9H?= =?us-ascii?Q?Je5zcoHI817I6JYG3ZzR0OIDGvqpCDFUWOwT6E/HuCw+2b8H3ev20ijVV0zC?= =?us-ascii?Q?hQQF/FpazyQhzpPuFGAhhAB3iITdFb5BG+kFLY5RWZ4uogToZHIcwLdg9V0H?= =?us-ascii?Q?DP9Vt/PIE7A3bgOIPYHOvDIEPl0V4pbbjXSH0ULE7Cc901AS/h6cGnoaaBHo?= =?us-ascii?Q?WeW4CqPfEsCDDPIbLYkDLsZsxHKaBOTaS6V5N+xx7QWFtz9cisCpU5/JWZQx?= =?us-ascii?Q?jutmXZYxCfy+vfe9Uc+YfMeT0BAZNqnPd0Yuc27wY2wgE2dtjADEuuJ4yWJr?= =?us-ascii?Q?m9QWz9LvlFjKI7MRu0N9E4XdlMGIRdB2wpQfKOYvdBEbqqivi4SFVaBAFf64?= =?us-ascii?Q?OOMvuu5w2LBJ+BQHuhFsimAELjshDGnNvJD7y7L1ztlYA8LchWYq2r4g1ucd?= =?us-ascii?Q?4wKSa7o8fKpc0C2zUL0ZiloeJ5/MvcmTr3ON?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2025 05:59:53.9990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e173b3d-b6a0-4717-554c-08dd848790cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4179 Add a new vEVENTQ type for VINTFs that are assigned to the user space. Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. Signed-off-by: Nicolin Chen --- include/uapi/linux/iommufd.h | 15 +++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index d69e7c1d39ea..d814b0f61fad 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1113,10 +1113,12 @@ struct iommufd_vevent_header { * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, }; /** @@ -1140,6 +1142,19 @@ struct iommu_vevent_arm_smmuv3 { __aligned_le64 evt[4]; }; +/** + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) + * + * The 128-bit register value from HW exclusively reflect the error bits for a + * Virtual Interface represented by a vIOMMU object. Read and report directly. + */ +struct iommu_vevent_tegra241_cmdqv { + __aligned_le64 lvcmdq_err_map[2]; +}; + /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_veventq_alloc) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 88e2b6506b3a..d8830b526601 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -292,6 +292,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) /* ISR Functions */ +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) +{ + struct iommufd_viommu *viommu = &vintf->vsmmu.core; + struct iommu_vevent_tegra241_cmdqv vevent_data; + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) + vevent_data.lvcmdq_err_map[i] = + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + &vevent_data, sizeof(vevent_data)); +} + static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) { int i; @@ -337,6 +351,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) vintf_map &= ~BIT_ULL(0); } + /* Handle other user VINTFs and their LVCMDQs */ + while (vintf_map) { + unsigned long idx = __ffs64(vintf_map); + + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); + vintf_map &= ~BIT_ULL(idx); + } + return IRQ_HANDLED; } -- 2.43.0