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Wed, 9 Jul 2025 12:02:04 -0700 Date: Wed, 9 Jul 2025 12:02:03 -0700 From: Nicolin Chen To: Vasant Hegde CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v8 14/29] iommufd/viommu: Add IOMMUFD_CMD_HW_QUEUE_ALLOC ioctl Message-ID: References: <49a93d92ce657cf6a0d588d2b31ad3600ace21f7.1751677708.git.nicolinc@nvidia.com> <1f18d7a3-b515-4096-aff5-1aea31ce4f7e@amd.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1f18d7a3-b515-4096-aff5-1aea31ce4f7e@amd.com> X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3E:EE_|IA0PPFD7DCFAC03:EE_ X-MS-Office365-Filtering-Correlation-Id: eedfd18b-933d-45a0-eec1-08ddbf1b20d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026|7416014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 19:02:19.0990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eedfd18b-933d-45a0-eec1-08ddbf1b20d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPFD7DCFAC03 On Mon, Jul 07, 2025 at 01:11:00PM +0530, Vasant Hegde wrote: > Hi , > > > On 7/5/2025 6:43 AM, Nicolin Chen wrote: > > Introduce a new IOMMUFD_CMD_HW_QUEUE_ALLOC ioctl for user space to allocate > > a HW QUEUE object for a vIOMMU specific HW-accelerated queue, e.g.: > > - NVIDIA's Virtual Command Queue > > - AMD vIOMMU's Command Buffer, Event Log Buffers, and PPR Log Buffers > > > > Since this is introduced with NVIDIA's VCMDQs that access the guest memory > > in the physical address space, add an iommufd_hw_queue_alloc_phys() helper > > that will create an access object to the queue memory in the IOAS, to avoid > > the mappings of the guest memory from being unmapped, during the life cycle > > of the HW queue object. > > > > AMD's HW will need an hw_queue_init op that is mutually exclusive with the > > hw_queue_init_phys op, and their case will bypass the access part, i.e. no > > iommufd_hw_queue_alloc_phys() call. > > Thanks. We will implement hw_queue_init[_iova] to support AMD driver and fixup > iommufd_hw_queue_alloc_ioctl(). Is that the correct understanding? Yes. I think just a simple "hw_queue_init" will be good as the object structure stores "iova" already: struct iommufd_hw_queue { ... u64 base_addr; /* in guest physical address space */ ... }; Thanks Nicolin