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X-CSE-ConnectionGUID: ryuPhG5RThi41PpMzAG2Vw== X-CSE-MsgGUID: P5ItKD/bQM+2EFzo4KGMHg== X-IronPort-AV: E=McAfee;i="6800,10657,11483"; a="71329432" X-IronPort-AV: E=Sophos;i="6.16,284,1744095600"; d="scan'208";a="71329432" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 08:45:29 -0700 X-CSE-ConnectionGUID: NnComOITQdK4pQxSKP4Mgw== X-CSE-MsgGUID: qu82479pRqauvpL6VVdZ8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,284,1744095600"; d="scan'208";a="154172233" Received: from smile.fi.intel.com ([10.237.72.52]) by orviesa009.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 08:45:25 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.98.2) (envelope-from ) id 1uXM7m-0000000CFHy-0sN8; Thu, 03 Jul 2025 18:45:22 +0300 Date: Thu, 3 Jul 2025 18:45:21 +0300 From: Andy Shevchenko To: Lothar Rubusch Cc: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, corbet@lwn.net, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, eraretuya@gmail.com Subject: Re: [PATCH v11 4/8] iio: accel: adxl345: add inactivity feature Message-ID: References: <20250702230315.19297-1-l.rubusch@gmail.com> <20250702230315.19297-5-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Thu, Jul 03, 2025 at 04:59:50PM +0200, Lothar Rubusch wrote: > On Thu, Jul 3, 2025 at 4:26 PM Andy Shevchenko > wrote: > > On Wed, Jul 02, 2025 at 11:03:11PM +0000, Lothar Rubusch wrote: ... > > > #define ADXL345_REG_TAP_SUPPRESS_MSK BIT(3) > > > #define ADXL345_REG_TAP_SUPPRESS BIT(3) > > > #define ADXL345_REG_ACT_AXIS_MSK GENMASK(6, 4) > > > +#define ADXL345_REG_INACT_AXIS_MSK GENMASK(2, 0) > > > +#define ADXL345_POWER_CTL_INACT_MSK (ADXL345_POWER_CTL_AUTO_SLEEP | ADXL345_POWER_CTL_LINK) > > > > > > #define ADXL345_TAP_Z_EN BIT(0) > > > #define ADXL345_TAP_Y_EN BIT(1) > > > #define ADXL345_TAP_X_EN BIT(2) > > > > > > +#define ADXL345_INACT_Z_EN BIT(0) > > > +#define ADXL345_INACT_Y_EN BIT(1) > > > +#define ADXL345_INACT_X_EN BIT(2) > > > +#define ADXL345_INACT_XYZ_EN (ADXL345_INACT_Z_EN | ADXL345_INACT_Y_EN | ADXL345_INACT_X_EN) > > > + > > > #define ADXL345_ACT_Z_EN BIT(4) > > > #define ADXL345_ACT_Y_EN BIT(5) > > > #define ADXL345_ACT_X_EN BIT(6) > > > > Now it's even more mess. I am lost in understanding which bits/masks are from > > the same offset and which are not. > > > > I'm sorry for that. I mean, while the above is supposed to make it > clear where the "values" are coming from, I also could setup something > like the following which is shorter. > +#define ADXL345_INACT_XYZ_EN GENMASK(2,0) > +#define ADXL345_ACT_XYZ_EN GENMASK(6,4) > > As I understand you, you'd rather prefer to see the latter one in the kernel? My personal preference can be found, for example, in drivers/pinctrl/intel/pinctrl-intel.c. But I'm not insisting to use _my_ schema. Just find a way how to group them semantically. -- With Best Regards, Andy Shevchenko