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X-CSE-ConnectionGUID: Y4A/bBFjRkGbhwpLpzLRBg== X-CSE-MsgGUID: SUa65eNUTui0E+7GAuNddA== X-IronPort-AV: E=McAfee;i="6800,10657,11666"; a="69353637" X-IronPort-AV: E=Sophos;i="6.21,214,1763452800"; d="scan'208";a="69353637" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2026 10:55:18 -0800 X-CSE-ConnectionGUID: 4r3rK8zgTNW2zA8Jo7XIaA== X-CSE-MsgGUID: zzGXgLS1TwaXJZjwuZfG0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,214,1763452800"; d="scan'208";a="234733637" Received: from abityuts-desk.ger.corp.intel.com (HELO localhost) ([10.245.244.157]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2026 10:55:15 -0800 Date: Fri, 9 Jan 2026 20:55:13 +0200 From: Andy Shevchenko To: rodrigo.alencar@analog.com Cc: linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, Jonathan Cameron , David Lechner , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet Subject: Re: [PATCH v3 2/6] iio: frequency: adf41513: driver implementation Message-ID: References: <20260108-adf41513-iio-driver-v3-0-23d1371aef48@analog.com> <20260108-adf41513-iio-driver-v3-2-23d1371aef48@analog.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260108-adf41513-iio-driver-v3-2-23d1371aef48@analog.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Thu, Jan 08, 2026 at 12:14:51PM +0000, Rodrigo Alencar via B4 Relay wrote: > > The driver is based on existing PLL drivers in the IIO subsystem and > implements the following key features: > > - Integer-N and fractional-N (fixed/variable modulus) synthesis modes > - High-resolution frequency calculations using microhertz (µHz) precision > to handle sub-Hz resolution across multi-GHz frequency ranges > - IIO debugfs interface for direct register access > - FW property parsing from devicetree including charge pump settings, > reference path configuration and muxout options > - Power management support with suspend/resume callbacks > - Lock detect GPIO monitoring > > The driver uses 64-bit microhertz values throughout PLL calculations to > maintain precision when working with frequencies that exceed 32-bit Hz > representation while requiring fractional Hz resolution. ... > +/* Specifications */ > +#define ADF41510_MAX_RF_FREQ (10000ULL * HZ_PER_MHZ) > +#define ADF41513_MIN_RF_FREQ (1000ULL * HZ_PER_MHZ) > +#define ADF41513_MAX_RF_FREQ (26500ULL * HZ_PER_MHZ) We need HZ_PER_GHZ. I think it's easy to have one be present in units.h. ... > +#define ADF41513_MIN_REF_FREQ (10U * HZ_PER_MHZ) > +#define ADF41513_MAX_REF_FREQ (800U * HZ_PER_MHZ) > +#define ADF41513_MAX_REF_FREQ_DOUBLER (225U * HZ_PER_MHZ) How does "U" help here? ... > +#define ADF41513_MIN_INT_4_5 20 > +#define ADF41513_MAX_INT_4_5 511 > +#define ADF41513_MIN_INT_8_9 64 > +#define ADF41513_MAX_INT_8_9 1023 Not sure if we want (BIT(x) - 1) for the limits as we have non-0 minimums. ... > +#define ADF41513_MAX_CLK_DIVIDER 4095 Sounds like a candidate for (BIT(12) - 1). ... > +#define ADF41513_MAX_PHASE_MICRORAD 6283185UL Basically I'm replying to this just for this line. 180° is PI radians, which is something like 31415926... Can we use here (2 * 314...) where PI is provided in one of the used form? This will help to grep and replace in case we will have a common PI constant defined in the kernel (units.h). -- With Best Regards, Andy Shevchenko