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Miller" , Donald Hunter , Eric Dumazet , Jonathan Corbet , Leon Romanovsky , Mark Bloch , Michal Schmidt , Paolo Abeni , Pasi Vaananen , Petr Oros , Prathosh Satish , Saeed Mahameed , Shuah Khan , Simon Horman , Tariq Toukan , Vadim Fedorenko , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org Subject: Re: [PATCH net-next v3 1/2] dpll: add fractional frequency offset to pin-parent-device Message-ID: References: <20260504155340.411063-1-ivecera@redhat.com> <20260504155340.411063-2-ivecera@redhat.com> <20260506183342.767b5fbc@kernel.org> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260506183342.767b5fbc@kernel.org> Thu, May 07, 2026 at 03:33:42AM +0200, kuba@kernel.org wrote: >On Mon, 4 May 2026 17:53:39 +0200 Ivan Vecera wrote: >> + At top level this represents the RX vs TX symbol rate >> + offset on the media associated with the pin. > >Isn't this a hacky hack? I'd think that pin is in or out. >Having a freq offset between two pins or pin and parent's >ref lock makes sense. This new interpretation sounds like >we are trying to shove a difference between two pins into one? The pin is in, but it is associated with SyncE port that has RX/TX symbol rate offset. As the doc says, the "offset on the media associated with the pin". Why is that hack? > >> @@ -299,6 +299,10 @@ zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, >> { >> struct zl3073x_dpll_pin *pin = pin_priv; >> >> + /* Only rx vs tx symbol rate FFO is supported */ >> + if (dpll) >> + return -ENODATA; >> + >> *ffo = pin->freq_offset; > >It's easy for driver authors to forget this sort of validation. >We should fail close, so it's better to have some "capability" >bits or something for the driver to opt into getting given format >of the call.