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From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@ziepe.ca>
Cc: Ashish Mhetre <amhetre@nvidia.com>, <catalin.marinas@arm.com>,
	<will@kernel.org>, <corbet@lwn.net>, <skhan@linuxfoundation.org>,
	<robin.murphy@arm.com>, <joro@8bytes.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<iommu@lists.linux.dev>, <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v7 2/3] iommu/arm-smmu-v3: Introduce CFGI/TLBI-repeat workaround infrastructure
Date: Fri, 17 Jul 2026 14:16:53 -0700	[thread overview]
Message-ID: <alqbxaKVYFX1BZR5@nvidia.com> (raw)
In-Reply-To: <20260717201841.GC701389@ziepe.ca>

On Fri, Jul 17, 2026 at 05:18:41PM -0300, Jason Gunthorpe wrote:
> On Tue, Jul 14, 2026 at 10:42:01AM +0000, Ashish Mhetre wrote:
> Because the VM has access to VCMDQ/etc it can issue commands directly
> (maybe not on this chip, but as a general comment), thus invalidation
> errata need to be made visible to the VM and we need to expect the VM
> will generate invalidations to properly deal with any errata.
> 
> Ie I'd expect the VM to see a "nvidia,tegra264-smmu" compatible string
> to activate the errata fix.
> 
> If so then we will already get duplicated invalidations here and then
> we will duplicate them again. That's not great.

Oh, that's a good point.

> On the other hand if you want to emulate a generic and actually
> functional SMMU device that has nothing like VCMDQ/etc then you must
> do something like this in this patch.

Tegra264 has virtualization use case. And It's built with VCMDQ,
which should be the default case than the generic vSMMU case.

> I was imagining a general direction that we would expose the errata
> information to the guest and the guest would have to deal with it.
> 
> Given this is the opposite I wonder if we want to do it. It does make
> sense for a chip that probably doesn't have vCMDQ and I don't think
> qemu can even create a DT description to trigger the errata anyhow.

I don't have the source code of the VMM used on Tegra264, but I
believe the guest kernel can be the same copy of kernel as the
host. So, its VMM is likely to use the "nvidia,tegra264-smmu" DT
compatible string, to trigger the errata at the guest level.

> But it starts to become confusing down the road if we decide other
> invalidation errata (like the CONT must be RIL thing) must be delt
> with by the guest.
>
> So.. Maybe add a comment why this one is different, or maybe just
> disable FEAT_NESTING if there isn't a use case?

Given the use cases on Tegra264, instead of patching the iommufd
path as this patch does, perhaps we should simply spit a WARN in
arm_vsmmu_init():

	if (static_branch_unlikely(&arm_smmu_erratum_repeat_tlbi_cfgi_key))
		dev_warn(smmu->dev,
			 "guest must WAR the repeat_tlbi_cfgi erratum\n");

?

Thanks
Nicolin

  reply	other threads:[~2026-07-17 21:17 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-14 10:41 [PATCH v7 0/3] iommu/arm-smmu-v3: Tegra264 invalidation workaround Ashish Mhetre
2026-07-14 10:42 ` [PATCH v7 1/3] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Ashish Mhetre
2026-07-17 19:59   ` Jason Gunthorpe
2026-07-14 10:42 ` [PATCH v7 2/3] iommu/arm-smmu-v3: Introduce CFGI/TLBI-repeat workaround infrastructure Ashish Mhetre
2026-07-17 20:18   ` Jason Gunthorpe
2026-07-17 21:16     ` Nicolin Chen [this message]
2026-07-14 10:42 ` [PATCH v7 3/3] iommu/arm-smmu-v3: Enable CFGI/TLBI-repeat workaround on Tegra264 Ashish Mhetre
2026-07-17 20:19   ` Jason Gunthorpe

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