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Wed, 22 Jul 2026 12:16:22 -0700 Date: Wed, 22 Jul 2026 12:16:22 -0700 From: Nicolin Chen To: Ashish Mhetre CC: , , , , , , , , , , , Subject: Re: [PATCH v8 3/3] iommu/arm-smmu-v3: Enable CFGI/TLBI-repeat workaround on Tegra264 Message-ID: References: <20260722102033.1122277-1-amhetre@nvidia.com> <20260722102033.1122277-4-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-doc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260722102033.1122277-4-amhetre@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E84:EE_|DS7PR12MB6189:EE_ X-MS-Office365-Filtering-Correlation-Id: f66b8ea2-0c1e-40e4-a41a-08dee825c412 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|1800799024|82310400026|23010399003|10067099003|11063799006|4143699003|56012099006|3023799007|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SU3xIr6b45lw1W3J+DaXPt4BZM5ssTwduXVef6kIqfEKZWT8p9MFZuzeP16x/upeIn0fDLrhaGmRRmoPOxwMFwbLeTFg2KliT9vMO9RCbeWO9mUam9n3Z+iLtY+7ZIWB+ReulcZuvD5rPTamcM+qptUH5Qr/noBJ0kYoUUzJbOlHaSlwR/Re4/Z9F4eOBLBNABogPwb+T2+bGhFwcPSe6NsoVw/MpV3KhNhpKLF3VyzlheAborRsbJ6NrAuDZy+ZrRf6qSmZQR+u6RgKaGPbONrWHnggRCtfYnsLnXxKvabeVUYLenCyBtQIvIIHmGeQluUbZHWdRgU8YkKF3qtlw0pENghQaPf1Ok089Y3pEsfuhbyebaFvBn1CS81YqDD7IPqTEfAD7UsPC9uW3HUGg9k+5oU0MmYl3PoCBjnIOCpChHUJp9jINO6yWcCGriPh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2026 19:16:43.3267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f66b8ea2-0c1e-40e4-a41a-08dee825c412 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E84.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6189 On Wed, Jul 22, 2026 at 10:20:33AM +0000, Ashish Mhetre wrote: > The host repeats only the invalidations it issues itself. On a nesting > setup the guest submits its own invalidations, either directly through > VCMDQ or via the iommufd user-invalidation path, so the guest is the one > that has to apply the workaround there. Report the erratum to user space > through the new IOMMU_HW_INFO_ARM_SMMUV3_ERRATA_REPEAT_TLBI_CFGI hw_info > flag so a VMM can confirm the guest runs a matching "nvidia,tegra264-smmu" > (or otherwise double the commands itself). The host therefore does not > repeat the guest's user-issued invalidations, which would otherwise be > doubled a second time. I think this "enable" patch is doing a bit too much. All the iommufd-related changes can be added separately I would do a cleanup: - arm-smmu-v3: Factor force_sync - arm-smmu-v3: Add arm_smmu_erratum_repeat_tlbi_cfgi_key and WAR - arm-smmu-v3-iommufd: Add IOMMU_HW_INFO_ARM_SMMUV3_ERRATA_REPEAT_TLBI_CFGI - arm-smmu-v3: Set arm_smmu_erratum_repeat_tlbi_cfgi_key > +/** > + * enum iommu_hw_info_arm_smmuv3_flags - Flags for ARM SMMUv3 hw_info > + * @IOMMU_HW_INFO_ARM_SMMUV3_ERRATA_REPEAT_TLBI_CFGI: If set, user space must > + * issue TLBI/CFGI+SYNC commands twice due to a hardware erratum T264-SMMU-3. > + * See the description at arm_smmu_erratum_repeat_tlbi_cfgi_key. You can follow the kdoc style as enum iommufd_option. Nicolin